Loongson Technology Develops Its Own CPU Instruction Set Architecture

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The end of Arm, MIPS, x86, RISC-V in China?

Loongson
(Image credit: HKEPC)
Anton Shilov
Anton Shilov
Contributing Writer

Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.

26 Comments Comment from the forums
  • setx
    Using RISC-V would be a nice move.
    Inventing their own ISA is only going to waste software development efforts.
    Reply
  • Pyrostemplar
    However, only time will tell whether the company can actually develop a competitive ecosystem for its LoongArch.

    As if it mattered in China. The Party just needs to make it mandatory.
    Reply
  • hotaru.hino
    setx said:
    Using RISC-V would be a nice move.
    Inventing their own ISA is only going to waste software development efforts.
    It's probably based on some existing ISA anyway and claiming it's some "brand new tech that will put the West to shame"

    Also it's China. They're willing to go through the trouble of shifting map coordinates around so satellite imagery doesn't match up with road maps for "national security"
    Reply
  • shady28
    "...it had developed its own CPU instruction set architecture (ISA), Loongson Architecture (LoongArch) that has nothing to do with architectures designed outside of China. "

    And we're supposed to believe that, why?
    Reply
  • InvalidError
    shady28 said:
    And we're supposed to believe that, why?
    Putting together your own ISA is easy enough, the really tedious part is figuring out what instructions are most useful and performance-critical, most of which achievable by profiling software on existing architectures. The rest is mainly a matter of coming up with your own names, an efficient operation encoding scheme and operand packing formats, then plugging all of that into a cross-compiler such as a customized GCC to spit out native binaries.

    An ISA is just the instruction set with supporting architectural features such as the registers and flags instructions can access, it isn't tied to any particular implementation in software emulators, re-compilers, FPGA implementations, silicon, etc. Anyone can write a minimalist one on a napkin if they wanted to, that isn't the hard part.
    Reply
  • shady28
    InvalidError said:
    Putting together your own ISA is easy enough, the really tedious part is figuring out what instructions are most useful and performance-critical, most of which achievable by profiling software on existing architectures. The rest is mainly a matter of coming up with your own names, an efficient operation encoding scheme and operand packing formats, then plugging all of that into a cross-compiler such as a customized GCC to spit out native binaries.

    An ISA is just the instruction set with supporting architectural features such as the registers and flags instructions can access, it isn't tied to any particular implementation in software emulators, re-compilers, FPGA implementations, silicon, etc. Anyone can write a minimalist one on a napkin if they wanted to, that isn't the hard part.

    You just spewed a bunch of garbage, you clearly don't know what an ISA is in this context.

    Meanwhile "LoongArch" is turning out to be a modified MIPS64 ISA where they've merely renamed some of the instructions.

    https://www.realworldtech.com/forum/?threadid=201588&curpostid=201593
    By: Ariadne Conill (ariadne.delete@this.dereferenced.org), April 16, 2021 10:53 pm

    "
    I did some digging into this, as I maintain the MIPS64 port in Alpine, and was planning to target Loongson at some point.

    From what I can tell, LoongArch is just a fork of the MIPS ISA, in a similar way to how MIPS32r5 and MIPS64r6 are backward-incompatible forks of the MIPS ISA. I conclude this based on the fact that LoongArch offers the same extensions that MIPS CPUs do, just with slightly different names, as can be seen in this translated press release. For example, what MIPS CPUs call the Virtualization Extension (VZ), LoongArch calls the LoongArch Virtualization Extension (LVZ). Another example is that the MIPS SIMD instructions (MSA) are renamed to LoongArch Vector Extension (LSX).

    Specifically, I believe LoongArch to be a fork of MIPS64r6. "
    Reply
  • InvalidError
    shady28 said:
    You just spewed a bunch of garbage, you clearly don't know what an ISA is in this context.
    There is no 'in this context' here, an ISA is just a set of definitions by definition. If China wants to rip off the open-source MIPS ISA and spare itself the trouble of writing their own together from scratch, more power to them.
    Reply
  • ginthegit
    shady28 said:
    You just spewed a bunch of garbage, you clearly don't know what an ISA is in this context.

    Meanwhile "LoongArch" is turning out to be a modified MIPS64 ISA where they've merely renamed some of the instructions.

    https://www.realworldtech.com/forum/?threadid=201588&curpostid=201593
    By: Ariadne Conill (ariadne.delete@this.dereferenced.org), April 16, 2021 10:53 pm

    "
    I did some digging into this, as I maintain the MIPS64 port in Alpine, and was planning to target Loongson at some point.

    From what I can tell, LoongArch is just a fork of the MIPS ISA, in a similar way to how MIPS32r5 and MIPS64r6 are backward-incompatible forks of the MIPS ISA. I conclude this based on the fact that LoongArch offers the same extensions that MIPS CPUs do, just with slightly different names, as can be seen in this translated press release. For example, what MIPS CPUs call the Virtualization Extension (VZ), LoongArch calls the LoongArch Virtualization Extension (LVZ). Another example is that the MIPS SIMD instructions (MSA) are renamed to LoongArch Vector Extension (LSX).

    Specifically, I believe LoongArch to be a fork of MIPS64r6. "
    From what I am reading, i think Titan's understanding of the ISA is actually accurate. Considering that the x86 and x64 along with the RISC achitectures are essentally the same thing just with different register access and optimised coding for the CISC.
    As an engineer who can write in Assember code directly (albeit simple code), I find that the old ISA is weak and slow and needed optimisations. For example using the MOV instruction is lagely pointless as it is just a simple instruction to load a register or offload a register to some other entry, and largely is for structural and internal coding. Because Mov is requred and written so many times within each instruction (for any high level language like C and Java), it can be incorporated (as is done with CISC instructions) to be written out of the coding as it is implied when any other function like ADD or IF statement is used, and it can always be assumed that the working register is Ax. It means that a New ISA can completely disregard it as a call and each instruction is hardwired.
    I have for a long time thought that there are many changes to the ISA which have been long awaited to make computers quicker and more efficient (in the same way that direct x 12 did to all its predecessors.
    Reply
  • setx
    InvalidError's position on the ISA is correct: it's trivial to create new ISA. But why almost no one does that? Because ISA without software for it is completely useless.

    It looks like they want to maintain some compatibility with MIPS with more extensibility:
    Instruction encoding is totally different than MIPS (more instruction formats) but (almost) all MIPS instructions can be translated to exactly one LoongArch instruction.

    So nothing outstanding from technical standpoint: not a breakthrough but also not a reinventing the wheel.
    Reply
  • ginthegit
    setx said:
    InvalidError's position on the ISA is correct: it's trivial to create new ISA. But why almost no one does that? Because ISA without software for it is completely useless.

    It looks like they want to maintain some compatibility with MIPS with more extensibility:


    So nothing outstanding from technical standpoint: not a breakthrough but also not a reinventing the wheel.

    It is a shame really, Making a new ISA would be an excellent idea to reduce the ability of hackers, and also reduce calls and latency. If an new internal registry system were to be built, an optimised ISA could be a game changer for Speed and process. It is the Whole idea of the advantages of CISC over RISC so why not.
    Compatibility with other ISA is not really necessasy if you create a compiler that can optimise the new code to be translated from the old code.
    Its something I dont understand. To get old programs to work on different platforms, you just force the source code through a compiler dedicated to the Chip and the ISA it understands. So getting Windows 10 to work on ARM is as simple as optimising the code through an ARM compiler. The only drawback is the speed at wheich it runs.
    Reply