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Report: TSMC's 5nm Process to Power Zen 4, Reportedly Already at 50 Percent Yield

(Image credit: TSMC)

The China Times reports that TSMC's upcoming 5nm process has already hit yields of 50%, meaning 50% of all processors yielded on a 5nm wafer are fully functional. The report also specifies that AMD's Zen 4 architecture will be fabbed on the 5nm process.

Although the yield rates have reportedly reached 50%, the other 50% of these dies are not totally broken but can be salvaged as processors with fewer cores enabled, for example. TSMC's 5nm is also entering risk production, which includes the very first wave of products that are expected to help iron out any kinks so TSMC can bring all of its 5nm capacity fully online.

The new 5nm node reportedly brings a 1.8x greater density over 7nm and 15% higher clock speeds at the same power, or reduce power consumption by 30% (meaning processor designers will have to choose one or a blend of both). This is not quite as good as the jump from 16nm to 7nm was, but as many are aware, silicon is reaching its limits rather soon, and we should expect density and power efficiency gains to slow down a little.

Two new processors, Apple's A14 and Hisilicon's new Kirin processor, have reportedly already been taped out on 5nm. The chips will supposedly be mass-produced in July. The China Times also points out AMD's Zen 4 CPUs will be based on 5nm. The node almost doubles density, so perhaps we might see a doubling in core count, though a 50% increase is more likely because 1.8x isn't quite 2x.

Zen 4 is, of course, quite a ways off, expected in 2021 at the earliest, and possibly even 2022. Since it is on a brand new node, it's easy to expect we will see some packaging difference between it and Zen 2/3. Perhaps AMD will increase the number of cores per die, or increase the number of dies and keep them all at eight cores each.

Meanwhile, Samsung and Intel (TSMC's only real competition), have been struggling to get out new nodes. Intel suffers the most and is still on its 2014 14nm process for the vast majority of its CPUs because its 10nm development was extremely troubled. Intel's 10nm process is finally live but the company only uses it for a handful of laptop CPUs, likely due to supply constraints.

Samsung is apparently going to manufacture Nvidia's upcoming 7nm GPUs, but that remains to be seen. It's not clear how well Samsung's 7nm process compares to TSMC's. TSMC certainly seems like the obvious winner today, but Intel isn't out of the race quite yet, as its highly anticipated 7nm process could bring the company back into the forefront of CPU manufacturing.

We can likely expect any processor sporting TSMC's upcoming 5nm process to be significantly ahead of any chip on an older process, though the lead won't be quite as pronounced as it used to be between a new node and an old node. Because of this, we can also expect that 5nm capacity will be in high demand just as 7nm is, so hopefully, TSMC has enough supply for the whole world to share.

  • InvalidError
    If density really doubles going from 7nm(+) to 5nm, AMD may need to double the entire CCD just to keep the chiplet size manageable. It would enable 8-16 cores mainstream CPUs to get made using a single CCD, which should simplify the whole design and reduce latencies all-around. By then, hex-cores should be fine getting demoted exclusively to APUs.
    Reply
  • bit_user
    InvalidError said:
    If density really doubles going from 7nm(+) to 5nm, AMD may need to double the entire CCD just to keep the chiplet size manageable.
    Okay, so you're talking about cores per chiplet (CCD = Core Complex Die).

    Do you foresee them increasing the CCX (i.e. Core Complex)? If so, do you think they'd go to 6 cores or 8?
    Reply
  • InvalidError
    bit_user said:
    Do you foresee them increasing the CCX (i.e. Core Complex)? If so, do you think they'd go to 6 cores or 8?
    The number of cores per CCX is already increasing with Zen 3 albeit with only one CCX per CCD instead of two if AMD's slides accurately depict that change and rumors say the L3 may be going up to 48MB to cash in on 7nm+'s improved density. Since the complexity of non-blocking structures usually scales with the square of endpoints, I'm going to guess first-gen 5nm won't be fast enough to support another doubling to 16-cores (3-4X the glue-logic between cores, L3 slices and fabric) without significant compromises so we'll have 8+8 instead, maybe on 5nm+ for 16 cores CCX. Would make sense for AMD to test a new process with a conservative CCX design (use two simpler CCXes per CCD to reduce the number of things that can go wrong) then merge CCXes into one after the process has matured some more.

    Feeding these things is going to get interesting once we reach 32-cores CCDs. We'll likely need to go NUMA with on-package HBM3 or similar at that point to relieve the CCD-IOD bottleneck.
    Reply
  • JamesSneed
    admin said:
    5nm is already yielding at 50%, making its ramp even faster than that of 7nm which was the fastest ramp at TSMC ever

    Report: TSMC's 5nm Process to Power Zen 4, Reportedly Already at 50 Percent Yield : Read more

    Nope unless we are talking about non logic chips like DRAM. This is going to be a bunch of nonsense just like the report AMD is moving chipsets to a third party.
    Reply
  • InvalidError
    JamesSneed said:
    This is going to be a bunch of nonsense just like the report AMD is moving chipsets to a third party.
    ASMedia has been involved in the design and manufacturing of all Ryzen chipsets except for the X570 so far and is also making the upcoming B550. The X570 designed in-house by AMD is the outlier, nothing surprising about AMD letting ASMedia handle the X670. AMD did the X570 in-house because ASMedia was not planning to have its PCIe4 ready for integration into Zen 2 chipsets in time. Hasty PCIe4 implementation is likely a signigicant part of X570's high TDP.
    Reply
  • DotNetMaster777
    Is there the report translate to English language ?
    Reply
  • Daniel Nenni
    Fake news. First of all you have no idea what TSMC yield is. Yield is a closely guarded secret and it is highly dependent on the design. Second, 5nm is in risk production (announced at the latest TSMC conference) and that would never happen at 50% yield. Third 5nm is now frozen for the Apple iProducts and that would never happen at 50% yield. Total click bait.
    Reply
  • drivinfast247
    Daniel Nenni said:
    Fake news. First of all you have no idea what TSMC yield is. Yield is a closely guarded secret and it is highly dependent on the design. Second, 5nm is in risk production (announced at the latest TSMC conference) and that would never happen at 50% yield. Third 5nm is now frozen for the Apple iProducts and that would never happen at 50% yield. Total click bait.
    Bam!

    I was gonna be a smartass and say something like "oh no, Daniel Nenni says it not true so that's that". Then I did a quick Google search and if this is really Daniel Nenni then he probably knows what he's talking about.
    Reply
  • Daniel Nenni
    Also, 7nm uses the 10nm fabs so yes ramp is much faster than a greenfield fab. TSMC 5nm and 3nm will also use the same fabs so expect the 3nm yield ramp to be faster than 5nm, absolutely.
    Reply