Ryzen 7 5800X3D Beats Ryzen 7 5800X By 9% In Geekbench 5

hotaru.hino said:

We can look back at AnandTech's deep dive on Zen 3 to get answers for this.
It's important to note that the L3 cache is a victim cache of L2. Basically, when L2 gets full, the oldest thing gets kicked out into L3. Also as a result, L3 cannot prefetch data.
Zen 3's increased cache came at a cost of higher latency and lower bandwidth per core. It was meant more to service multi-core workloads, since this allows every core in the CCX to have the same latency when accessing each other's data
They made the observation that the L2 TLB is only 2K entries long, with each entry covering 4KiB. This means per core, the TLB can only cover 8MiB of L3 cache. So a single core has issues even without the extra cache from V-CacheThere's also another issue: you can only have so much cache before you'll spend too much time looking through cache than it would've taken to look it up from RAM.

For example if we look at this chart from AnandTech's article:
https://images.anandtech.com/doci/16214/lat-5950.png(note the y-axis is logarithmic)

If we assume the latency is linear after 16MiB, which appears to be 15ns in the worst case, and L3 cache gets full, you're now looking at 90ns just to look through the whole thing. It would've been faster to go look at RAM at that point.

Yes you make valid points and you are certainly learned in the sci-art of micro architecture, however I would like to correct a few things you bring up that might help you understand why bigger L3 is helpful in certain cpu workloads. First, the ram latencies you are referencing (less than 90ns) are the best case scenario IE data is requested on an open active row and column which is prepped to be read. This is almost never the case. Aida 64 and other latency and bandwidth benchmarks always give the best case latency for cache and ram so you must take each to be equivalent in how their respective latencies react to different data locations IE my ryzen 9 5950x L3 has a 10.4ns latency according to Aida 64 but as the graph you provided shows worst case is closer to 90ns. The same goes for RAM, my cas 14 3800mhz ram has an Aida 64 latency of 60.2ns but worst case is closer to 1 us or more due to row precharge, access, read, etc. duties to find and transfer the data + a trfc refresh cycle that can halt the data fetch in its tracks and cause the fetch to restart.

Second, a victim cache (unlike inclusive cache) is simply a term used to describe an overflow cache. You are correct that the oldest data in L1/2 gets booted to L3 but second, just as important, is if the jobs data is too big for L1/2 (which often is the case) the L3 acts as a slower L2 cache extension to allow more of the needed data for the job at hand from having to be continually fetched from the much slower ram then eliminated from cache from disuse only for the deleted data a microsecond or so later being re-fetched from RAM again due to many workloads re-using the same data multiple times (obviously like you said, if said data value is popular it will stay in L2 but if it’s disused for more than a couple microseconds then it is booted into L3 and eventually deleted as L2 continues to push disused data into L3, thus having more L3 prolongs the disused data life in cache in case it’s called upon again, which happens more often than you think). Thus, as I surmised in my answer, having more L3 cache helps with multi core workloads by making ram access a rarer instance while feeding the cores with more consistent data flow. That is why the single core scores are very similar between the 2 ryzen 5800 series cpus (because the data for 1 cores job is small enough to fit in the 5800x’s L1/2/3 but not big enough to fit all the data needed to drive 16 independent jobs at the same time. The 5800x3d has enough L3 to fit more of geekbench’s 16 thread workload and thus limits the amount of ram accesses. That is why AMD claims that the v-cache improves gaming performance while suffering from lower clock frequency. If a game thread can be kept fed with low latency cache accesses instead of high latency ram accesses then the cpu core wastes less clock cycles waiting for the required data and thus gets more done on average per clock cycle.

Any way, I hope you don’t take my rebuttal in the wrong light, you do make valid points but microarchitectures are very complex and thus their behaviors are complex as well. Unless you study architectures for a living it’s harder to gain detailed knowledge.

Actually the results are not surprising. In fact, I feel AMD should not even bother about releasing a stop gap solution here because in my opinion, this offers too little performance uplift, and too much of a price increase for most users. While it is true that Intel have regained their performance crown, but the most important thing is price. Zen 3 may be older, but if the price is right, it is still a viable option. But for USD 449, which is basically the launch price of the R7 5800X, the performance uplift is uninteresting/ unexciting, so I doubt they will see any improvement in sales, nor will they be able to retain the performance crown.

watzupken said:

Actually the results are not surprising. In fact, I feel AMD should not even bother about releasing a stop gap solution here because in my opinion, this offers too little performance uplift, and too much of a price increase for most users. While it is true that Intel have regained their performance crown, but the most important thing is price. Zen 3 may be older, but if the price is right, it is still a viable option. But for USD 449, which is basically the launch price of the R7 5800X, the performance uplift is uninteresting/ unexciting, so I doubt they will see any improvement in sales, nor will they be able to retain the performance crown.

I don't think it is a stop gap, but more of a prototype test. If this works well in real world use and with consumers, the tech can be used in future processors, with lowered prices and better performance. If it doesn't, this will be the first and last 3D V-Cache CPU.

Probably should have just cancelled this thing after the initial engineering samples didn't pan out. I doesn't look like from these early benchmarks this chip fits in anywhere, especially since it can't be overclocked at all.

salgado18 said:

I don't think it is a stop gap, but more of a prototype test. If this works well in real world use and with consumers, the tech can be used in future processors, with lowered prices and better performance. If it doesn't, this will be the first and last 3D V-Cache CPU.

The problem I'm seeing is AMD hyped this up to be some sort of game changer and it'll bring it appreciable performance upgrades over the non V-cache CPUs. While I don't disagree they wanted to throw this tech out on something to see how it works, I think they should've released it with less fanfare.

Phillip Corcoran said:

Graphics Command Centre.

hotaru.hino said:

The problem I'm seeing is AMD hyped this up to be some sort of game changer and it'll bring it appreciable performance upgrades over the non V-cache CPUs. While I don't disagree they wanted to throw this tech out on something to see how it works, I think they should've released it with less fanfare.

If you can get 9-15% IPC gain without an architectural change, then it's a win for consumers. If they put 3D cache on future chips and try to solve the lower clock speed issues. Then it's a winning feature. It's at the point where it's showing great promise, but it's not a game changer unless the cpu clock can match current offerings.