The Intel Haswell-X Xeon EP processor made an appearance in a visit from VR-Zone’s Nebojsa Novakovic to one of Intel’s facilities in Penang, Malaysia during Intel’s “Design in Asia” tour. The processor appears to be the Socket 2011-3 Haswell EP or Xeon E5 v3 and features 14 cores, a 35 MB cache, twin 9.6 GT/s QPI channels, and support for quad channel DDR4-2133 memory.
Even though the processor is still at least a year from commercial announcement, and the Ivy Bridge EP chips will only be arriving this summer, it seems that Intel’s Haswell Xeons have already reached at least the QS phase. Selected customers may be receiving fully working ES versions by the end of the year.
I heard the Steamroller based Opteron 6400 series (codenamed "Warsaw") will still only have 16 Cores at maximum, and considering the 16 core Opteron 6300s are no match for the Sandy Bridge E5s on the clock for clock (16 cores vs 16 threads), AMD will have to worry about their diminishing server CPU share.
Also there is hardly anything that needs so many cores/threads and isn't already running on a server.
^ This, but I think it also has a lot to do with (surprisingly) IBM, and TDP. Competition with IBM in certain server and HPC markets is driving Intel towards parallel computing and greater core counts within the same TDP, even at the expense of clock frequency. This is because the main performance factors in many of these workloads is core count and not GHz. Efficiency is also very important, so if it's a choice between an 8 core ~3.0 GHz, or a 6 core ~3.5 GHz within a 130W TDP, the choice is very clear (at least for Xeons). The same cannot be said for i7's, where competitive clock frequencies are still very important due to workloads that are typically not nearly as parallel (such as games).
LGA2011 i7's also have to compete with LGA1155/1150, and Intel doesn't want a situation where their mainstream processors completely blow away their prosumer processors in lightly threaded workloads. This is another reason they have to keep those clock frequencies up.
They are also separated for yield reasons. The LGA2011 chips are much, much larger than their LGA-1155 counterparts in terms of transistor count and subsequently are much larger in surface area as well when fabricated on the same node. This results in fewer chips per wafer and a greater number of defects per chip. This means that SB-E/IB-E chips that come off the fabrication line with all cores and all cache segments working flawlessly are rare compared to their quad-core-only counterparts.
If you look at price ranges between GT2 and GT3, you can see that GT3 models are only ~$30 (10%) more expensive than their nearest GT2 equivalents despite GT3 being ~50% larger - 177sqmm vs ~260sqmm. I would take this as a clear indication that die size is a relatively minor factor in Intel's pricing scheme - most of the markup is mainly due to the good old "because they can."
Since Intel has so much slack between their real costs and retail prices on i5 and up, they could easily afford adding 2-4 cores to i5/i7 without changing price points if they really wanted or needed to. Individual cores are pretty small compared to L3 cache and IGP: Haswell's x86-64 cores are around 10sqmm each; you could fit around eight of those in the extra die space between GT2 and GT3.
The way it goes for Xeon is this: pre-silicon -> ES0 -> ES1 -> ES2 -> QS -> Production
QS is the last step before production, and for Xeon EP CPUs it typically comes ~4-6 months before the launch date. For EX Xeons testing phases are considerably longer due to RAS features.
Also, Ivy Bridge EP comes with different die variants (high core count, etc.) so 4960X is not castrated 12-core 269x v2, but it comes from lower-core count dies.
I do not know the reason why Intel does not put more cores on consumer i7, but I suppose it has something to do with the fact that in the consumer space there are simply no "killer apps" for more than 6 cores and the single-core frequency often means much more to the consumer due to crappy consumer software/games not optimized properly to use multiple cores.
Business factors probably play a role too but I guess not as much as with the SNB-EP (yields should not be the issue with Ivy Bridge EP due to different dies with low core count, as it was the case with SNB-EP where 3930/3960x/3970x were originally 8-core dies with 2 cores fused off). Probably the lack of proper competition from AMD does not help either.
Another thing to think about is overclocking - I suppose significant proportion of consumers for the HEDT Core i7 segment are overclocking. While the TDP of 12-core Xeon is still 130W, this is so only because the clock is kept comparatively low compared to i7. If Intel would allow voltage manipulation and overclocking of the 12-core part, it is quite easy to blow the TDP off the chart (probably well over 500W) by irresponsible overclocking (say, pushing the VCC to 1.45v and multiplier to 48x+) - this would probably damage most motherboards, and also it would require mandatory requirements to be much more expensive in terms of voltage regulation circuitry. Even with all precautions, there would be much more fried motherboards and this is bad for marketing.