AMD’s Data Center Roadmap: EPYC Genoa-X, Siena Announced, Turin in 2024

AMD revealed its CPU server roadmap at its Financial Analyst Day 2022 and also unveiled 4th-Gen EPYC Genoa-X processors with 3D V-Cache, the edge and telecommunications-focused EPYC Siena, and AMD's first data center APU, the MI300X. In addition, AMD teased the 5th-gen EPYC Turin chips that will launch before the end of 2024.

AMD EPYC CPU Server Roadmap

Here we can see the AMD server roadmap until the end of 2024. We also have the CPU core roadmap in the second slide, which you can read more about here. The server CPU roadmap shows a significant expansion of AMD's target markets with the 4th-Gen EPYC family. These chips all come with the Zen 4 microarchitecture. This microarchitecture will also power consumer chips, too, like the Ryzen 7000 series. 

AMD will now have general-purpose server chips with its standard EPYC Genoa silicon, a high-performance optimized EPYC Genoa-X with 3D V-Cache, cloud-optimized chips with the 128-core 256-thread Bergamo, and edge- and telecommunications-focused Siena processors. It is though that all of the Zen 4 chips drop into the same SP5 socket. Further below, we'll dive into these new chips, including AMD's first data center APU, the Instinct MI300.  

AMD announced that the 5th-generation EPYC Turin family will come to market in 2024 but didn't divulge any further details. The CPU core roadmap does tell us that Turin will come in 4nm and 3nm, and also in 3D V-Cache and cloud-optimized variants. 

The 128-core 256-Thread Bergamo and 96-Core Genoa

AMD shared a demo of a 96-core EPYC Genoa providing a >75% uplift over the current-gen EPYC flagship in a Java SPECjbb benchmark. This gain comes from the move to the 5nm Zen 4 architecture, along with the 12-channels of DDR5 memory.  That’s not to mention the extra 32 cores over the previous-gen EPYC. Genoa is also notable for supporting PCIe 5.0 and CXL-attached memory, like we see with Samsung's 512GB CXL memory Expander. AMD says Genoa remains on track for launch in the fourth quarter of this year.

The 128-core Bergamo comes with the density- and scale-out optimized Bergamo comes with up to 128 Zen 4c cores and an astounding 256 threads in a single socket. Bergamo drops into the same SP5 socket as the Genoa processors and supports the full Zen 4 ISA.

The Zen 4c cores are conceptually similar to the efficiency cores (e-cores) that we see with other types of chip architectures in both Arm and x86 flavors. These 'c' cores are smaller than the standard Zen 4 core that will debut in Genoa, with certain unneeded functionality removed to improve compute density. The chips have a density-optimized cache hierarchy to increase core counts, thus addressing cloud workloads that need higher thread density. This could mean that the chips have a smaller cache(s), or perhaps a cache level has been removed, but AMD hasn't shared details. The Zen 'c' cores support the full Zen 4 ISA — unlike Intel does with Alder Lake, AMD won't disable some features like AVX.

AMD EPYC Genoa-X and Siena

(Image credit: AMD)

AMD revealed that it will have a version of its upcoming EPYC Genoa processors that will come armed with up to 1+ GB of L3 cache. The 5nm Genoa-X processors will come with up to 96 cores, just like the standard Genoa products, and drop into the same socket. In effect, these are the Zen 4 equivalents to the 3D V-Cache equipped EPYC Milan-X processors. 

AMD is also expanding into the telecommunications and edge markets with its new Siena, a streamlined chip architecture with up to 64 Zen 4 cores on offer. AMD hasn't shared many details on these chips yet, but they are optimized for power efficiency and represent an important expansion of AMD's addressable market. AMD's EPYC has already dealt a devastating blow to Intel's Xeon D in some applications, and we imagine Siena will further that advantage. This chip will probably drop into the same SP5 socket as the rest of the EPYC chips, but 12 channels of DDR5 might not make sense for these types of space- and power-constrained environments, so there is probably more than meets the eye to the Siena chips.

We're sure to learn more soon. Both Genoa-X and Siena arrive in 2023. 

AMD Instinct MI300 APU - Zen 4 Meets CDNA 3

(Image credit: AMD)

The 5nm AMD Instinct MI300 is the company’s first APU for the data center, meaning it will have both x86 CPU and GPU cores integrated onto the same chip package. AMD uses the 4th-gen AMD infinity Architecture to tie together the Zen 4 CPU cores and CDNA 3 GPU cores with a coherent memory interface. The chip uses 3D packaging tech, with CPU, GPU, cache, and HBM in the single-chip package, but it isn’t clear if all of these components are stacked vertically or that only certain components are 3D-stacked. AMD claims this accelerator provides up to an 8X performance increase in AI workloads over the MI250X. You can read more about this chip here.

Paul Alcorn
Managing Editor: News and Emerging Tech

Paul Alcorn is the Managing Editor: News and Emerging Tech for Tom's Hardware US. He also writes news and reviews on CPUs, storage, and enterprise hardware.

  • jp7189
    96 cores is an interesting number. Can they really cram 12+1 chiplets on the package or are they changing to 12 cores ccds?