At the ISSCC 2020 conference, French research institute CEA-Leti showed a 96-core processors created from six chiplets, connected via an active interposer.
The work was shown this week at the IEEE Solid-State Circuits Conference (ISSCC) in San Francisco and reported on by IEEE Spectrum. CEA-Leti stacked six 16-core chiplets on an active interposer, which is a large piece of silicon that connects the individual chiplets. The active interposer contains voltage regulation circuits and a network-on-chip (NoC) for linking the on-chip SRAM memories together.
All together, the chip had a power consumption of 156mW per square millimeter. No additional specs of the chip were given.
Active Interposer
The NoC has a bandwidth of 3TBps per square millimeter of silicon, with a latency of just 0.6ns per millimeter. Meanwhile, for the voltage regulation circuits, it used more-efficient switched capacitor voltage regulators instead of low-dropout regulators. Those usually require off-chip capacitors, but this was not needed because of the active interposer, as they could be integrated.
Active interposers are not common yet in commercial designs, except for Intel’s Foveros in Lakefield. The more widely-used passive interposers only provide power and interconnection capabilities. However, CEA-Leti’s scientific director argued that active interposers are the way forward for a mix-and-match chiplet ecosystem:
“If you want to integrate chiplets from vendor A with chiplets from vendor B, and their interfaces are not compatible, you need a way to glue them together,” he said. “And the only way to glue them together is with active circuits in the interposer.”
Chiplet designs have become more and more in fashion over the last several years. Notable designs include Xilinx Virtex VU19P, Intel Stratix 10 GX 10M FPGA, Barefoot Networks’ Tofino 2 and AMD’s Zen 2 lineup. Intel has been most active in trying to foster an industry-wide chiplet ecosystem, most notably for its Agilex FPGAs.
