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Intel Starts Shipping 10nm Agilex FPGAs

(Image credit: Intel)

Intel announced on Thursday that it had begun shipments of the first of its 10nm Agilex FPGAs to early access customers, including Microsoft. Intel says they will use it to create solutions for networking, 5G and accelerated data analytics.

With the announcement, Intel follows in the footsteps of its competitor Xilinx, who started shipping its next-gen Versal ACAPs roughly two months ago. We provided a comparison of the products at the time. Despite being later than the once-promised second half of 2018, Intel is surely going to like the fact that it has practically erased the gap of roughly a year it had at the 16/14nm generation.

When Intel acquired Altera in 2016, the story it liked to tell was that the FPGA company that moved earlier to a new process node tended to have the most market share that generation, and hence that one of the benefits of Intel was that it could leverage its process technology lead to gain share on Xilinx. With the two companies now neck and neck, other merits will likely decide in whose favor the market share will swing.

Intel says that the participants of the early access program include Colorado Engineering Inc., Mantaro Networks, Microsoft and Silicom. Microsoft said it plans to use Agilex in a number of its upcoming projects. Dan McNamara, SVP of the recently formed Networking and Custom Logic Group (formerly the Programmable Solutions Group) at Intel, pitched Agilex as follows:

“The Intel Agilex FPGA product family leverages the breadth of Intel innovation and technology leadership, including architecture, packaging, process technology, developer tools and a fast path to power reduction with eASIC technology. These unmatched assets enable new levels of heterogeneous computing, system integration, and processor connectivity and will be the first 10nm FPGA to provide cache-coherent and low latency connectivity to Intel Xeon processors with the upcoming Compute Express Link.”

Intel introduced Agilex in April as we detailed, but its changes can be summarized as follows:

  • 10nm process and EMIB 3D SiP packaging to support a custom logic continuum: integrate analog, memory, custom computing, custom I/O and Intel eASIC (structured ASIC) device tiles
  • The first FPGA to support Compute Express Link (CXL) for a low latency, memory coherent interconnect to future Xeon Scalable processors
  • 2nd generation HyperFlex architecture for 40% higher performance or 40% lower power
  • ~2x DSP floating-point performance, or 4x (up to 40TFLOPS) using the newly supported FP16 and BFLOAT16 data formats
  • Support for (up to) DDR5, PCIe 5.0, HBM3 and 112G transceiver speeds