Intel's next-generation Sierra Forest processors, designed for the Birch Stream-AP (BHS-AP) platform, are rumored to launch towards the end of 2023. Today, according to a listing on industry tool provider Li Tang Technology's website, we've learned that Intel will purportedly use an LGA 7529 CPU socket with 7,529 pins to host the upcoming processors.
Intel's Sapphire Rapids processors, which come early next year, will use an LGA 4677 socket with 4,677 pins. Compare that to the monstrous amount found on the BHS-AP, and you might wonder what those extra pins are used for.
Inside the LGA socket, there are various types of pins: some provide power to the processor, while others carry data. As processors use more advanced protocols, newer communication standards, and more power, the number of pins increases. Hence the constant need for more pins. As such, the BHS-AP's 7,529-pin socket certainly implies there will be plenty of new functionality and/or power delivery.
When it comes to Intel's server execution strategy, the BHS-AP platform won't arrive for a bit longer. First comes the Sapphire Rapids lineup in early 2022. According to recent unofficial reports, Emerald Rapids will arrive at the end of that year. In the early beginning of 2023, Granite Rapids should come in SP and AP variants as the first 7 nm designs designed for the Birch Stream platform. It's thought that, towards the end of that same year, Intel plans to deliver Sierra Forest AP designs on the BHS-AP platform.
Additionally, the listing mentions the code name Ruby Rapids as well as Diamond Rapids, which are all very distant solutions. The lineup seems to be a bit confusing so far, leaving us to wait and see which products reach the market, and when.
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I see rumors of zen4 Genoa chips with 12 memory channels. Intel's Sapphire Rapids is rumored to have 8 ddr5 memory channels, but also four stacks of HBM memory, which could be configured as additional memory channels. We could get more details in August from the Hotchips presentation on Sapphire Rapids.Reply
The Habana Gaudi architecture seems to be what is needed for ai/hpc processing... lots of IO relative to core count, and removing the L3 bottleneck. However, looks like Intel wants to use IPUs for the ethernet IO and funnel everything to the XPUs with PCIE/CXL.