Intel has hired Dr. Gary Patton, who most recently served as GlobalFoundries chief technology officer (CTO). He will lead Intel’s design enablement. The executive change was reported by Reuters on Wednesday, who saw an internal Intel memo.
Executive Roles at IBM and GlobalFoundries
Patton is a seasoned executive in the semiconductor business. From 2005 to 2015, he spent ten years at IBM Microelectronics. This included two years as vice president of technology development and design enablement, followed by eight years managing IBM’s 1600-person semiconductor R&D organization where he was responsible for the development of IBM’s semiconductor portfolio of processes and packaging technologies, design enablement and their high-volume ramp.
Until most recently, he was CTO and senior vice president of GlobalFoundries’ R&D and design enablement, where his focus was on developing differentiated technologies through design-technology co-optimization (DTCO) and collaboration with customers. Under his leadership, GlobalFoundries announced in 2018 that it had decided to cease 7nm and beyond process development, possibly by some combination of yield issues, development and fab costs and AMD’s switch to TSMC for its 7nm CPUs.
Instead, the company would focus on further development of its 14nm node by enhancing it with capabilities such as RF and embedded memory, and continue its investment in FD-SOI processes. Most recently, the company announced its 12LP+ process to compete on power and performance with small processes. According to his LinkedIn profile, Patton also drove a 6x reduction in design enablement critical bug rates and a 2x increase in bug resolution time.
Leading Process Enablement at Intel
At Intel, he will likely drive similar efforts since he will serve as corporate vice president and general manager of design enablement. Design enablement is a critical part in process development, responsible for the development of processes’ design rules and creation of process design kits (PDKs), tools and IP. This also involves partnering with electronic design automation (EDA) companies.
For example, Intel has cited as one of the key pillars of 7nm that it has a 4x reduction in design rules, helping to simplify and accelerate product development and time to market. As case in point, Intel hopes to transition a “full portfolio of products” to 7nm within a year of its launch and has also disclosed its intention to make its IP less process-dependent. It was also one of the drivers of Intel’s hyperscaling at 10nm.
Intel hiring Dr. Patton as outside semiconductor executive comes in the aftermath of multi-year delays it experienced at 10nm, which caused the company to stop its renowned Tick-Tock model and lose its status as leading edge semiconductor manufacturer to TSMC. In October, Intel CEO Bob Swan said the company vies to recapture process leadership by moving back to a two-year Moore's Law cadence.
On Wednesday, an Intel process roadmap that outlines the company's goals for the next decade came into public attention. Undoubtedly, Patton will play a role in ensuring that vision becomes reality.
He will report to Intel CTO Michael Mayberry.
It is not the first time in recent years the company has hired key executives from outside ranks. Once known for its practice of promoting from within, the change started with chief engineering officer Murthy coming from Qualcomm in 2015, at a time when the company was pivoting its focus from mobile to the data center and adjacent businesses.
At the highest ranks, he was joined by current CEO Bob Swan in 2016 as CFO, Tom Lantzsch from Arm (IoT) and Raja Koduri from AMD (processors and graphics) in 2017, Jim Keller from Tesla in 2018, and chief marketing officer (CMO) Karen Walker from Cisco in 2019. A few others include Naveen Rao, Amnon Shashua, and Craig Barratt from Intel’s acquisitions of Nervana, Mobileye, and Barefoot Networks.