JEDEC Updates DDR5 Standard: Improved Performance and Reliability

Just days before the first high-volume DDR5-supporting platforms are set to hit the market, JEDEC published an update to the standard that adds a set of features designed to improve yields, performance, and reliability of DRAM ICs. In addition, JESD79-5A expands specifications for DDR5-5600 and DDR5-6400 memory modules. 

"The fact that this update to DDR5 is being published so soon after the initial launch of DDR5 in July 2020 underscores JEDEC's ongoing commitment to continual improvement, and represents a collective effort on the part of all involved member companies to better serve the industry," said Mian Quddus, JEDEC Chairman. 

The original JESD79-5 specification defines how DDR5 SDRAM works and includes various features to enable long-term performance scaling as well as improved yields and the reliability of memory chips that operate at high frequencies and support high data transfer rates. The renewed spec adds several complementary capabilities that are designed to further improve yields, performance, and reliability.  

The added features include bounded fault error-correction support, Soft Post-Package Repair (sPPR) undo and lock, Memory Built-In Self-Test Post Package Repair (MBIST and mPPR), Adaptive RFM, and an MR4 extension. 

Producing DRAMs that work at high frequencies and support high data transfer rates is hard. Producing fast high-capacity chips with decent yields using leading-edge process technologies is even harder, so it is very reasonable for DRAM makers to add various self-test and repair capabilities. To some degree, these new features will somewhat reduce the cost of high-performance/high-capacity DRAMs for their manufacturers. But for now expect the prices of actual chips and modules to depend on supply and demand rather than on their costs.  

Since DDR5 is set to remain with the industry for years to come, adding features and enhancing the standard makes a lot of sense. Meanwhile, as it usually happens with new specifications, it remains to be seen how rapidly all DRAM makers will incorporate all the new features.  

"Samsung is proud to see that DDR5 memory will be able to reach new heights in operating efficiency and self-correcting capabilities, something that we and other industry leaders have been working intently to standardize over the past 14 months," said Young-Soo Sohn, vice president of the DRAM Memory Planning/Enabling Group at Samsung Electronics. "With these enhancements, the industry is setting an extremely firm foundation for one of the most ambitious memory upgrades ever ― an advancement particularly important for large server systems." 

In addition to adding new features, JESD79-5A expands the timing definition and transfer speed of DDR5 up to 6400 MT/s for DRAM core timings and 5600 MT/s for IO AC timings. This will help the industry to build an ecosystem of for upcoming DDR5-5600 platforms.  

AMD, Intel, Micron, Montage, Samsung, and SK Hynix have endorsed the additions to DDR5 introduced by the JESD79-5A specification. 

"With the new JESD79-5A DDR5 standard, JEDEC offers the most advanced memory for high performance and reliability and continues our joint commitment to enabling the best possible experiences for end users," said Joe Macri, Chief Technology Officer, Compute and Graphics Business Unit, AMD.