Libre-SOC Releases First Non-IBM OpenPOWER Chip in Decade

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Manufactured on TSMC's 180 nm Process

Libre-SOC Layout
(Image credit: Libre-SOC)

The Libre-SOC project, a team of engineers and creative personas aiming to provide a fully open System-on-Chip, has today posted a layout that the team sent for chip fabrication of the OpenPOWER-based processor. Currently being manufactured on TSMC's 180 nm node, the Libre-SOC processor is a huge achievement in many ways. To get to a tape out, the Libre-SOC team was accompanied by engineering from Chips4Makers and Sorbonne Université, funded by NLnet Foundation.

Based on IBM's OpenPOWER instruction set architecture (ISA), the Libre-SOC chip is a monumental achievement for open-source hardware. It's also the first independent OpenPOWER chip to be manufactured outside IBM in over 12 years. Every component, from hardware design files, documentation, mailing lists to software, is open-sourced and designed to fit with the open-source spirit and ideas.

The project is not just the CPU, but rather a development of a complete solution. The OpenPOWER CPU is accompanied by a custom-developed 3D processing suite that combines GPU (Graphics Processing Unit) and VPU (Video Processing Unit). The 3D pipeline can process most modern video codecs and it has support for Vulkan API.

The SoC will integrate everything needed to power a small embedded system and equip it with open-source hardware and software working seamlessly with custom open-source drivers.

The test ASIC is a combination of 130,000 logical gates packed on a 5.5 x 5.9 mm2 area. The engineers behind it implemented the OpenPOWER ISA v3.0B specification, which is just the current form of the design. Thanks to Imec's MPW Shuttle Service, the chip is getting manufactured on TSMC's 180 nm node, which represents a sufficient solution for this type of chip.

Multiple prototypes of the Libre-SOC chip are expected before we get a final product, with each new test ASIC having additional features. The next steps for the project include adding and enabling Cray-style vector extensions (SVP64), used for enabling efficient vector processing in hardware. For more details, please head over to Libre-SOC's website. More details and development credits can be found on the OpenPOWER blog.

Aleksandar Kostovic
4 Comments Comment from the forums
  • hotaru.hino
    Every component, from hardware design files, documentation, mailing lists to software, is open-sourced and designed to fit with the open-source spirit and ideas

    And this is how "open hardware" should be. It's one thing to list your BOM but have all of the components still contain chips and other IP made with proprietary ISAs or implementations. It's another to be able to make something that you could take, tweak, and submit to a fab.
    Reply
  • Kamen Rider Blade
    I wish it was on GloFlo 12nm instead of TSMC 180nm.

    -_-
    Reply
  • artk2219
    Kamen Rider Blade said:
    I wish it was on GloFlo 12nm instead of TSMC 180nm.

    -_-

    You gotta walk before you can run my friend, as the need for performance and volume increases and theres a chip that will benefit from the lower node im sure they'll make the switch.
    Reply
  • Lsjvvvvvv
    Kamen Rider Blade said:
    I wish it was on GloFlo 12nm instead of TSMC 180nm.

    -_-
    Did you even read the article? The architecture is only 130k logical gates in size, let's just assume 5(I know, I know not all logic gates requires that much transistor or uses that few transistor and that there are resistors etc but let's just assume 5 transistor) transistors per logic gate, 130k x 5 = 650k transistors. GloFo 12nm has a transistor density of 36Million Transistors in a single mm2, 650k Transistor is only ~2% of 36Million, so the 650k design would only use 2% of a millimeter, smaller than a speck of dust :neutral: I have no idea how are you going to route and connect dozens to hundreds of BGA traces through something the size of a speck of dust. 😑
    Reply