Samsung Foundry had started the initial production of chips using its 3GAE fabrication process, the company announced today. The new 3GAE (3nm-class gate-all-around early) manufacturing technology is set to improve performance, cut down power consumption, and increase transistor density. However, to do so, early designs must be tailored for the node, which essentially means that 3nm GAA is not for everyone just yet.
"Samsung Electronics, the world leader in semiconductor technology, today announced that it has started initial production of its 3-nanometer (nm) process node applying Gate-All-Around (GAA) transistor architecture," the statement from the company reads.
Samsung brands its 3GAE gate-all-around field-effect transistors (GAAFETs) as multi-bridge channel field-effect transistors (MBCFETs). The transistors' reduced leakage current is one of the key features, as the gate is now surrounded by the channel across all four sides. Another advantage is that thickness of the channel(s) can be regulated to boost performance and/or lower power consumption. In theory, this is what 3GAE is all about, but it isn't that simple.
Based on the press release by Samsung Foundry (SF), its 3GAE process can reduce the power consumption of a chip by up to 45% at the same density and frequency. It can improve performance by 23%, given the same complexity and clocks, and reduce an IC area by 16% (assuming the same chip) compared to SF's 5nm-class nodes (we presume 5LPP).
Previously the company compared its 3GAE production node to its own 7LPP process, and the PPA (power, performance, area) numbers were by far more impressive, but this time around, we seem to be talking about a very specific case. Here is a quote from Samsung:
"In addition, the design flexibility of GAA is highly advantageous for Design Technology Co-Optimization (DTCO), which helps boost Power, Performance, Area (PPA) benefits. Compared to 5nm process, the first-generation 3nm process can reduce power consumption by up to 45%, improve performance by 23% and reduce area by 16% compared to 5nm, while the second-generation 3nm process is to reduce power consumption by up to 50%, improve performance by 30% and reduce area by 35%."
This specific case is called DTCO, and for those of us watching AMD (before it went fabless in 2009) and Intel closely, it is very familiar: DTCO is the technique of tailoring the standard cells and circuits of a chip design to the capabilities of a certain process technology to maximize performance, lower power, and reduce costs. The power, performance, and area advantage numbers that Samsung Foundry mentions for 3GAE already consider these optimizations, which is probably typical for the company's Early nodes. These technologies are generally aimed at Samsung at large, and also include certain early adopters seeking a particular benefit out of the PPA equation and willing to invest in DTCO.
DTCO is a very expensive endeavor, and very few companies are willing to invest in it. In the case of Samsung (at large), its Samsung LSI (chip development division) is one such customer. And yet contrary to the company's statement from late April about 'mass production' on GAA 3nm process, Samsung now only says it has entered into 'initial production.'
The 'initial production' term can be interpreted differently (i.e., an early start of mass production, when the first wafers are just entering the pipeline). But a promising sign is that Samsung's electronic design automation (EDA) tools partners — Ansys, Cadence, Siemens, and Synopsys — are ready with their software supporting 3nm GAA nodes (which currently includes 3GAE and 3GAP processes, with the latter expected in 2023).
Yet no matter where exactly Samsung's 3GAE is in terms of volume manufacturing, Samsung Foundry can be officially branded as the world's first producer of chips featuring gate-all-around transistors.
