Samsung Foundry will be the first maker of semiconductors to start using gate-all-around field-effect transistor (GAAFET)-like structures with its upcoming 3 nm fabrication process. The node is not quite ready for primetime yet, but at the IEEE International Solid-State Circuits Conference (ISSCC) engineers from Samsung Foundry shared some of the details about the upcoming 3 nm GAE MBCFET (multi-bridge channel FET) manufacturing technology.
Formally, there are two types of GAAFETs: typical GAAFETs called nanowires that feature 'thin' fins as well as MBCFETs called nanosheets that use 'thicker' fins. In both cases, the gate material surrounds the channel region on all sides. Actual implementations of both nanowires and nanosheets heavily depend on design, so in general many industry observers describe both with one term, GAAFETs. But previously they were known as surrounding-gate transistors (SGTs). Meanwhile, MBCFET is a trademark of Samsung.
The first GAAFETs were demonstrated in 1988, so the key advantages of the technology are pretty well known. The very structure of this type of transistor allows designers to precisely tune them for high performance or low power by adjusting width of the transistor channel (also known as effective width, or Weff); wider sheets enable higher performance at higher power while thinner/narrower sheets reduce power consumption and performance. To do something similar with FinFETs, engineers have to use additional fins in a bid to improve performance. But in this case the 'width' of the transistor channel can only be doubled or tripled, which is not really precise and sometimes inefficient. In addition, adjustments of GAAFETs allow for increased transistor density, as different transistors can be used for different purposes.
Back in 2019, Samsung's 3GAE process design kit version 0.1 included four different nanosheet widths to provide some flexibility for early adopters, though it is unclear whether the company has added more widths for extra flexibility. In general, Samsung says that when compared to its 7LPP technology, its 3GAE node will enable an up to 30% performance improvement (at the same power and complexity), up to 50% lower power (at the same clocks and complexity), and an up to 80% higher transistor density (which includes a mix of logic and SRAM transistors).
Samsung's 3GAE (its first-generation MBCFET technology) is due in 2022. So Samsung has not disclosed all of its peculiarities just now. At ISSCC, the company discussed how it improved SRAM performance and scalability using its new types of transistors. The scalability of SRAM has been lagging scalability of logic in recent years. Meanwhile, modern system-on-chips use loads of SRAM for various caches, so improving its scalability is a crucial task.
At ISSCC, Samsung Foundry described its 256Mb MBCFET SRAM chip with a 56mm2 die size, reports EE Times Asia. This means that while the company has yet to tape out its first 3GAE logic chip it is evident that the technology works for SRAM.
SRAM is a six-transistor memory cell: two pass gates, two pull ups, and two pull downs. In FinFET designs, an SRAM cell would use the same transistors with the same channel width. With MBCFET, Samsung could tune the channel width, so it came up with two schemes: In one case it used transistors with wider channels for pass gates and pull downs, while in another it would use transistors with wider channels for pass gates and transistors with narrower channels for pull downs. By using transistors with wider channels for pass gates and transistors with narrower channels for pull ups, Samsung has managed to decrease writing voltage by 230 mV compared to a regular SRAM cell, according to Samsung via IEEE Spectrum.