First truly 3D chip fabbed at US foundry, features carbon nanotube transistors and RAM on a single die — future devices could have up to 1000x improvement in energy-delay product

A collaborative research team has demonstrated what it says is the first monolithic 3D integrated circuit manufactured at a commercial U.S. foundry, reporting substantial performance gains over conventional flat chip designs. The prototype was developed by engineers from Stanford, Carnegie Mellon, the University of Pennsylvania, and MIT, and fabricated in partnership with SkyWater Technology.

The chip departs from conventional two-dimensional layouts by stacking memory and logic directly on top of one another in a single, continuous process. Instead of assembling multiple finished dies into a package, the researchers built each device layer sequentially on the same wafer using a low-temperature process designed not to damage underlying circuitry, resulting in a dense network of vertical interconnects that shortens data paths between memory cells and compute units.

The prototype was manufactured on SkyWater’s 200mm production line, using a mature 90nm to 130nm process. The stack integrates conventional silicon CMOS logic with resistive RAM layers and carbon nanotube field-effect transistors, all fabricated under a thermal budget of about 415°C. According to the team, early hardware tests show roughly a four-fold improvement in throughput compared with a comparable 2D implementation operating at similar latency and footprint.

Twelve-fold performance improvements seen in simulations

Beyond the measured hardware results, the researchers also evaluated taller stacks through simulation. Designs with additional tiers of memory and compute showed up to a twelve-fold performance improvement on AI-style workloads, including models derived from Meta’s LLaMA architecture. The group further argues that the architecture could eventually deliver 100-fold to 1,000-fold improvements in energy-delay product, a combined metric of speed and efficiency, by continuing to scale vertical integration rather than shrinking transistors.

While academic labs have previously demonstrated experimental 3D chips, the team emphasizes that this work differs in being built in a commercial foundry environment rather than a bespoke research line. SkyWater executives involved in the project described the effort as proof that monolithic 3D architectures can be transferred into domestic manufacturing flows, rather than remaining confined to university cleanrooms.

"Turning a cutting-edge academic concept into something a commercial fab can build is an enormous challenge," said co-author Mark Nelson, vice president of technology development operations at SkyWater Technology.

The team presented their research at the IEEE International Electron Devices Meeting (IEDM 2025) between December 6 and 10.

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