Intel details progress on fabbing 2D transistors a few atoms thick in standard high volume fab production environment — chipmaker outlines 300-mm fab compatible with integration of 2D transistor contacts and gate stacks
2D transistors based on 2D materials have been demonstrated in academia and research labs for more than a decade, but none of these demonstrations were compatible with high-volume semiconductor manufacturing, as they relied on small wafers, custom research tools, and fragile process steps. But this week, Intel Foundry and imec demonstrated a 300-millimeter–ready integration of critical process modules for 2D field-effect transistors (2DFETs), indicating that 2D materials and 2DFETs are moving closer to reality.
Modern leading-edge logic process technologies — such as Intel's 18A, Samsung SF3E, TSMC's N2 — rely on gate-all-around (GAA) devices, and all leading chipmakers are also developing complementary FETs (CFETs) to vertically stack transistors to extend density gains beyond what is possible with GAA. CFETs are considered the next step beyond gate-all-around transistors and are expected to emerge in the next decade. However, Intel and other chipmakers argue that continued scaling will eventually push silicon channels to their physical limits, where electrostatic control and carrier mobility degrade due to extremely small dimensions. To address this, the industry is increasingly evaluating 2D materials, which can form channels only a few atoms thick while maintaining strong current control.
Intel and Imec presented a paper at IDM that details their work on the family of transition-metal dichalcogenides (TMDs). In the demonstrated structures, WS₂ and MoS₂ were used for n-type transistors, while WSe₂ served as the p-type channel material. Although these compounds have been studied for years, the main challenge has been integrating them into a 300-mm wafer fab flow without damaging the fragile channels or relying on processing steps that cannot be reliably performed in a high-volume manufacturing environment.
The core innovation presented by Intel and imec is a fab-compatible contact and gate-stack integration scheme. Intel grew high-quality 2D layers and capped them with a multilayer stack of AlOx, HfO₂, and SiO₂. Then a carefully controlled selective oxide etch — a process that is conceptually similar to traditional interconnect fabrication — enabled formation of damascene-style top contacts. This step preserved the integrity of the underlying 2D channels, which are highly sensitive to contamination and physical damage.
This damascene top-contact approach addresses one of the most difficult challenges in 2DFET development: forming low-resistance, scalable contacts using processes compatible with production tools. Alongside the contacts, Intel and imec also demonstrated manufacturable gate-stack modules, a major hurdle that has historically prevented 2D devices from achieving industrial integration.
The importance of this joint work by Intel and imec doesn't lie in immediate productization, as 2D transistors based on 2D materials belong to the long-term future, perhaps in the second half of the 2030s or even in the 2040s. The value of the work is more about de-risking the development and eventual production of chips that will rely on 2D materials. By validating contact and gate modules in a production-class environment, Intel Foundry enables customers and internal design teams to evaluate 2D channels using realistic, scalable process assumptions rather than idealized lab environments. This approach is intended to accelerate device benchmarking, compact modeling, and early design exploration.
For now, Intel's strategy is to treat 2D materials as a future option that can be assessed well before silicon reaches its ultimate limits. By co-developing processes with partners like imec and exposing them to fab-like constraints early, Intel hopes to solve the challenges associated with their manufacturing early, avoiding late-stage surprises when new materials are finally needed.
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For Intel Foundry, the announcement sends two important messages. Firstly, Intel Foundry continues to conduct long-term research on technologies that will be needed years, if not decades, away, meaning that it will have solutions for the semiconductor industry in the 2030s or 2040s, and, therefore, is a reliable manufacturing partner. Secondly, Intel shows that even at the research stage, new transistor concepts must be developed with manufacturability in mind.
Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.
I wish much, much more ressources would be allocated to ferroelectricity and spintronics architectures, e.g: Spintec FESO
FESO (Ferroelectric–Spintronic) devices offer several fundamental advantages over conventional silicon CMOS transistors.
Unlike CMOS, which is inherently volatile and requires continuous power to retain state, FESO devices are intrinsically non-volatile. Information is stored directly in the physical state of the device (ferroelectric polarization and magnetization), enabling instant-on operation and near-zero standby power.
Moreover, FESO naturally combines memory and computation in the same device. In CMOS systems, logic and memory are physically separated, leading to the well-known von Neumann bottleneck and excessive data movement. FESO eliminates much of this overhead by enabling in-memory and stateful computation, dramatically improving energy efficiency.
Another key advantage is that FESO supports both analog and digital operation. Synaptic weights for AI can be stored and updated incrementally in an analog manner using device physics, while the same technology can also operate digitally when required. This flexibility is extremely difficult to achieve with CMOS transistors alone.
Finally, FESO enables continuous, local learning AI. Because weights are persistent and updated directly at the device level, learning does not require frequent access to external volatile memory or global weight refresh. This opens the door to always-on, adaptive, brain-like systems that are fundamentally out of reach for purely CMOS-based architectures.
In short, while CMOS excels at fast, deterministic digital logic, FESO introduces persistence, statefulness, and co-located memory and computation—properties that are essential for the next generation of energy-efficient and continuously learning AI hardware.
