SiFive Envisions 128-Core RISC-V SoCs as Gap With x86 and Arm Closes

SiFive emerged from stealth mode as a developer of small, low-power cores for microcontrollers in 2016. By late 2020, the company had a chip that could run Linux and this week said that it developed a CPU core that is comparable to modern offerings designed by Intel and Arm. The company believes that such high-performance designs could be used for a wide variety of applications, including server-grade system-on-chips with 128-cores.

SiFive's next-generation high-performance core "is within reach of Intel's Rocket Lake family […] and Arm's Cortex-A78 design […] in terms of single-core performance," James Prior, senior director of product marketing and communications at SiFive, told The Register. The details are scarce at the moment, but Prior implies that the next generation core is architecturally similar to its existing Performance P550 design, but is enhanced in all directions to extract higher performance.

SiFive's Performance P550: Fast

Earlier this year SiFive introduced its new Performance-series P550 general-purpose core based on the company's 64-bit U84 microarchitecture with a 13-stage, triple-issue, out-of-order pipeline that is aimed at multi-core application processors. The P550 core features private 2x32KB L1 and 256KB L2 caches, a data precision FPU with bit manipulation extensions, and support for multicore coherence configurations with up to four cores with a unified 4MB L3 cache in a core complex. 

The company claims that the P550 core measures 0.23 mm2 when implemented in a 7 nm fabrication process and can operate at around 2.40 GHz. As for performance, the P550 delivers a SPECINt 2006 score of 8.65/GHz, which is comparable to performance of contemporary Arm and x86 cores. Meanwhile, SiFive says that the P550 offers a three times performance uplift per mm2 compared to Arm's Cortex-A75.

The P550 is available for licensing from SiFive. Since this is only a CPU core, licensees can add all kinds of special-purpose accelerators, IP, and I/O interfaces to them to get a unique system-on-chip that will address their needs (or targeted market segments/workloads).

SiFive's Performance P550: Furious… With up to 128 Cores per SoC

SiFive's next-generation core for performance demanding applications seems to be based on a very similar microarchitecture as the P550, but this one is actually a quad-issue out-of-oder microarchitecture with a higher performance per clock. In addition to a wider issue, the future core will also have larger L1 caches (up to 128KB), and up to 2MB private L2 cache. In addition, it supports multicore coherence with up to 16 cores with 16MB L3 cache in a complex.  

SiFive claims that the next-gen Performance core can offer 50% higher performance compared to the P550. Furthermore, it will be possible to scale designs all the way to 128 cores and address performance-hungry applications. Since SoCs with 128 cores are used in virtualized environments, the core also adds features like hypervisors and interrupts. Meanwhile, with performance-per-core on par with Arm's and Intel's latest microarchitectures, SiFive's next-generation core could address high-performance computing (HPC) applications over time, just as envisioned by RISC-V International, the organization that oversees the development of the RISC-V instruction set architecture. Though, we would expect HPC customers to want something more proprietary from SiFive.

Available Next Year

James Prior says that the next generation core will be available as an RTL deliverable next year. Customers will also be able to test drive the core on FPGA models.