TSMC announced (opens in new tab) a partnership with Broadcom to introduce an enhanced Chip-on-Wafer-on-Substrate (CoWoS) platform, a 2.5D integrated circuit (2.5D IC) through-silicon via (TSV) interposer-based packaging technology, that supports the industry’s first and largest full 2x reticle size interposer.
The next generation CoWoS interposer (opens in new tab) has an area of approximately 1,700mm2 and can be used to boost computing power for high-performance computing (HPC) systems. The technology will also be ready to support TSMC’s next-generation 5nm process node.
The new CoWoS generation can accommodate multiple logic system-on-a-chip (SoC) dies and up to six cubes of high-bandwidth memory (HBM) supporting up to 96GB of memory. The new CoWoS technology also provides 2.7 terabytes per second (TB/s) bandwidth, which is 2.7x higher than TSMC’s previous CoWoS technology that it launched in 2016.
TSMC also says the interposer provides 2.2X more memory bandwidth than any other competing technology. According to WikiChip, Intel’s cancelled Spring Crest (opens in new tab) had a memory bandwidth of 1.23 TB/s, while NEC’s Aurora peaks at 2.2 TB/s.
The support for the larger memory bandwidth comes from Samsung’s “Flashbolt” HBM2E dies (opens in new tab). These dies have twice the density (16 gigabits) per die compared to competing solutions and support up to 3.2 GT/s. That results in a bandwidth of 2.46 TB/s for six stacks.
The higher memory capacity and bandwidth makes it suited for memory-intensive applications such as deep learning, 5G networking workloads, power-efficient data centers, and so on. The new technology offers additional space and increased flexibility and yield for complex ASIC designs.
TSMC has been previewing interposer technology with up to 3x the reticle size (2500 mm2) or even larger, but there’s no word on when we can expect this technology to arrive.