According to a report by Phoronix, the world's first laptop operating on the RISC-V instruction set, called ROMA, has gone up for preorder. DeepComputing and Xcalibyte will produce ROMA in China. The laptop features a quad-core RISC-V processor, up to 16GB of LPDDR4/LPDDR4X memory, and up to 256GB of storage, with support for RISC-V and most Linux operating systems.
The ROMA marks a significant milestone in the RISC-V community. The architecture has not received wide adoption in the consumer space; it's more prevalent in the server industry. However, unlike conventional consumer laptops, this RISC-V model will target developers using the RISC-V instruction set for app development so that it will have very little use as a traditional laptop.
According to the DeepComputing press release, the laptop will use a "world's first" 12nm/28nm SoM package. The chip will include four cores and a GPU and NPU for 3D/2D and AI acceleration. Only 100 ROMA laptops will be available, and all are available for preorder now. Each ROMA will feature a unique NFT, and you can have your name or company name engraved on the notebook if desired.
RISC-V is a rather old instruction set by today's standard but has only recently received wide adoption by the computer industry. RISC-V has many advantages over mainstream instruction sets like x86, AMD64, and ARM. The largest of them is full open-source licensing so anyone can utilize the architecture. It is radically different from x86 and ARM, which require commercial licenses and fees for companies to acquire and use the technology.
From a performance standpoint, the most differentiating feature of RISC-V compared to x86 and AMD64 is the use of a more simplistic RISC architecture instead of CISC.
RISC or Reduced Instruction Set Computer follows the idea of using simple instructions completed in a single clock cycle. The disadvantage of this technique is that it requires more code to complete an executed task, but the advantages are improved battery life and energy efficiency. (If you were wondering, ARM chips also use RISC over CISC to improve battery life on mobile devices, but its implementation is far different.)
CISC, or Complex Instruction Set Computer, is the opposite of RISC. Instead of completing instructions in a single clock cycle, the goal is to complete tasks in as few lines of code as possible, which frequently means instructions will take multiple clock cycles to complete. It results in higher energy consumption, but it is more advantageous to developers since CISC requires less code altogether.
RISC-V is perfectly capable of being used in the consumer space; however, competition from other instruction sets has relegated it to the enterprise markets. Nearly all chips built on RISC-V cater to HPC, AI, or other high-level computing tasks, but RISC-V can break out of the mold if more laptops and desktops come out featuring these types of chips. The ROMA might appease developers, but there's no stopping users from using the laptop for other tasks.
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had to ruin a good thing with NFT :|Reply
Huh? RISC-V is literally the newest ISA on the planet; author needs to do his homework. (I was on the RISC-V team at Berkeley).Reply
Yeah it's like <Mod Edit> all over an interesting product.hotaru251 said:had to ruin a good thing with NFT :|
article was cringy. RISC-V is among the newest being only a bit over a decade old. Yes it's based on an older design from the 80's but ARM, Intel, and AMD's are even older. You might say it's about the age or slightly older than MIPS...Reply
Also, the 'RISC takes more code' is ambiguous and is a bit amateur talk. Yes, RISC binaries (ie, machine code) is larger, but the 'code' isn't. ie, it's an identical amount of code for an application on arm, risc, intel etc as the compiler handles the conversion to machine code. Saying it uses more code for risc is like... maybe correct in a very narrow scope of 'code'... but definitely not in the common vernacular. No one would say x64 requires more code than x86 for example, and x64 binaries are larger from the same input code.
I would not expect this from Tom's.
Where is the guy that was arguing with me about RISC-V getting no investment money...Reply
I'm curious how far Risc-V will go. I feel fairly confident it will be pretty dominant in the areas that don't require record breaking performance, like all sorts of microcontrollers. I've always liked the idea of public domain.Reply
SunMaster said:I'm curious how far Risc-V will go. I feel fairly confident it will be pretty dominant in the areas that don't require record breaking performance, like all sorts of microcontrollers. I've always liked the idea of public domain.
Do you know who spear headed/lead/started the whole EUV thing? It all began several decades ago in the US with a little something called the EUV-LLC initiative....which has members such as the DOE/Intel/AMD/Micron to research and commercialize EUV......Guess who signed a contract with the EUV-LLC to gain tremendous progress and advantage over rival japan(who ultimately failed to do their own EUV)? That's right a little company called ASML......Which is why the US can stop a Dutch based company to sell EUV machines to China. Now you know......
Fdchdfa said:Do you know who spear headed/lead/started the whole EUV thing? It all began several decades ago in the US with a little something called the EUV-LLC initiative....which has members such as the DOE/Intel/AMD/Micron to research and commercialize EUV......Guess who signed a contract with the EUV-LLC to gain tremendous progress and advantage over rival japan(who ultimately failed to do their own EUV)? That's right a little company called ASML......Which is why the US can stop a Dutch based company to sell EUV machines to China. Now you know......
I think you posted to the wrong thread.
" ... use of a more simplistic RISC architecture ..."Reply
You mean "simpler," not "simplistic." A simplistic thing is too simple for purposes. "Simplistic" is a bad thing.
Also, this article was not up to snuff, in ways others have noted.