New X-NAND Flash Tech Doubles Flash Write Speeds

X-NAND
X-NAND (Image credit: Neo Semiconductor)

 The company behind X-NAND flash memory claims to have doubled the speed of its storage for its second generation of chips, as reported by Blocks and Files, by enabling data writes in parallel. This way, X-NAND can deliver SLC levels of performance from QLC flash, which is cheaper and comes in larger capacities.

Neo Semiconductor’s X-NAND architecture can be applied to all generations of flash memory and involves dividing each plane of the 3D matrix into four to 16 sub-planes, each of which can be accessed in parallel, using page buffers to optimize speed. Gen 2 X-NAND (PDF) takes this idea and compresses it down, using one plane to write to another, whereas before, it would have used three planes to write to a fourth. See our feature here for a fuller write-up of how the technology works.

Ian Evenden
Freelance News Writer

Ian Evenden is a UK-based news writer for Tom’s Hardware US. He’ll write about anything, but stories about Raspberry Pi and DIY robots seem to find their way to him.

  • hotaru251
    qlc price/size with slc speed...thats great.

    though i assume they WILL increase prices just cause they can for end user ;/
    Reply
  • bit_user
    I wonder what it does for heat/power. Seems like you might need a lot more cooling. Also, heat generally hurts the longevity of flash memory.

    Not to diminish their accomplishments, but I'm just wondering what's the catch.
    Reply
  • bit_user
    hotaru251 said:
    though i assume they WILL increase prices just cause they can for end user ;/
    The prices will necessarily be higher, because the flash which employs it must license Neo's IP.
    Reply
  • Alvar "Miles" Udell
    I'm wondering if this will have any real world effect though. For high demand applications, the durability of SLC and TLC is needed, which come with high speeds and already have solutions which max out the PCIe bandwidth, like Sabrent's 8 slot NVMe PCIe card. For consumer applications, where even direct-to-flash QLC drives have speed exceeding most people's internet download speed and read speed and cost per GB is most important, this will have no effect except to increase the price due to license fees. Even if this were an open standard with no license fee, there's little incentive for most manufacturers to implement it until at least the PLC or even the SexLC era due to lack of need, and that's not going to be for years, sadly.
    Reply
  • bit_user
    Alvar Miles Udell said:
    For consumer applications, where even direct-to-flash QLC drives have speed exceeding most people's internet download speed
    What an odd metric. Did you know that hard drives also have speeds faster than most people's internet download speed?
    Reply
  • Alvar "Miles" Udell
    bit_user said:
    What an odd metric. Did you know that hard drives also have speeds faster than most people's internet download speed?

    It is A metric yes, and an important one when you are discussing QLC and higher flash, especially at relatively small capacities where the SLC buffer can fill during a large program or game download and revert to the much slower direct to flash, which is slower than the sequential write capabilities of most 7200rpm HDDs, but if you were going off of just one metric, then you would choose a HDD.
    Reply
  • jp7189
    So, how does the compare to pseudo-slc in consumer drives today? Assuming it's comparable, then this really only helps in corner case when the drive is also full and any write cache is overwhelmed.

    I also wonder how this tech affects endurance and bit errors.
    Reply
  • bit_user
    jp7189 said:
    So, how does the compare to pseudo-slc in consumer drives today?
    They're not mutually exclusive, from what I understand.

    jp7189 said:
    Assuming it's comparable, then this really only helps in corner case when the drive is also full and any write cache is overwhelmed.
    Yes, that's where you'd see the biggest impact.

    jp7189 said:
    I also wonder how this tech affects endurance and bit errors.
    Good questions. I'm not sure we'll ever know, but I'd expect probably not much.
    Reply