The GNU Compiler Collection has gained support for AMD's upcoming Zen 5 architecture with a new patch, indicating a handful of new instructions will be coming to Zen 5-based chips (via Phoronix). Not only is the update an indication that AMD is steadily preparing Zen 5 for launch, but the particular instructions flag where AMD is seeking to take its brand-new architecture.
Interestingly, the compiler update indicates Zen 5 will debut five instructions never-before-seen on Zen-based chips. Four of the instructions have been native to Intel CPUs for a few years now, and one will be coming to the company's Granite Rapids server CPUs sometime shortly, so in a sense AMD is playing catch-up with Intel. That's not entirely unusual, as AMD doesn't seem to prioritize instruction set support as much as Intel, especially with regard to AVX-related instructions.
Perhaps the most notable of the five instructions is AVX-VNNI, which Intel first introduced with its 2021 Alder Lake CPUs. VNNI stands for Vector Neural Network Instructions, and it's become increasingly relevant in today's AI-focused environments. AVX-VNNI isn't to be confused with AVX512-VNNI, it is more powerful relative to the banner of AVX512 instructions. Both instructions can perform the same operations, but AVX512-VNNI has access to 512-bit vectors and EVEX extensions for even better performance.
Zen 4 already has AVX512-VNNI, so adding support for a weaker version may seem pointless, but Intel did the same thing years ago. The benefit of using the non-512-bit version may be for consumer parts, which could run software that doesn't take advantage of AVX512 the same way data center programs do. In any case, it seems certain that AMD is continuing to focus on AI with its future CPUs (including consumer models), which isn't that surprising.
The latest GCC patch isn't the first we've seen that adds support for Zen 5 CPUs. Zen 5 code has been trickling in since July of last year, and there was an update to Linux that added new power management features. For reference, GCC support for Zen 4 was added until after Ryzen 7000 processors had already launched, and although that shouldn't be taken as a sign that Zen 5 is right around the corner, it does probably mean it is launching sometime this year. AMD has hardly talked about Zen 5 thus far, but it may break its silence at its upcoming Computex presentation in May.
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AVX is unusable, because there is no standard. Each processor has different instructions.Reply
New processors do not support older instructions. Even the same CPU doesn't support the same instructions on all cores. Is a hell.
The only thing that can be trusted to work is SSE4.2, which is almost 2 decades old, but is even supported in ARM and smartphones.
I think you are referring to AVX-512, for which that is more or less true.yeyibi said:AVX is unusable, because there is no standard. Each processor has different instructions. Even the same CPU doesn't support the same instructions on all cores. Is a hell.
It is because of that irregularity that Intel decided to renumber the sets as AVX10.
Intel issued a microcode update that disabled the AVX-512 instructions on the CPUs where all cores did not support it.
New processors do not support older instructions.AVX is supposed to have been supported on new Intel and AMD CPUs since 2011. AVX2 since 2015.
Is there any of those instructions that doesn't work on some newer processor, or did you only refer to a subset of AVX-512?
Do you mean to running intel code in emulation on ARM64?yeyibi said:The only thing that can be trusted to work is SSE4.2, which is almost 2 decades old, but is even supported in ARM and smartphones.
Apple's Rosetta supports up to SSE4.2.
ARM does otherwise not run Intel instructions.
x86-64 code on Windows is supposed to use the CPUID instruction to check what is supported before it tries to use an instruction set extension. Mac OS has API calls for the same purpose.
Linux distributions have instead standardised on four "Microarchitecture levels" to compile against so that code wouldn't have to.
As @Findecanor said, you presumably mean AVX-512. In that case, the common baseline is basically what Skylake-X had. In the Linux universe, they blessed that as level 4 of the x86-64 ISA pyramid, so to speak, making it a fairly standard compilation target.yeyibi said:AVX is unusable, because there is no standard. Each processor has different instructions.
The AVX-512 instructions not implemented by newer CPUs are pretty much just some of those found in Xeon Phi, which was a specialty HPC product and thus not an issue for most software out there.yeyibi said:New processors do not support older instructions.
That's actually not true. Intel never supported heterogeneous ISA, even though there were hacks to enable it in the early days after Alder Lake launched.yeyibi said:Even the same CPU doesn't support the same instructions on all cores. Is a hell.
First, AVX & AVX2 are trustworthy, in that any CPU which supports them will implement them fully and consistently. Their biggest issue is just that the E-cores prior to Gracemont (e.g. Jasper/Elkhart Lake, Gemini Lake, Apollo Lake, etc.) didn't support them.yeyibi said:The only thing that can be trusted to work is SSE4.2, which is almost 2 decades old, but is even supported in ARM and smartphones.
Leaving that aside, SSE4.2 didn't ship until November 2008, which is 15.25 years ago - not really almost 2 decades.