YouTube channel Moore's Law Is Dead leaked two new allegedly official AMD slides detailing key specifications and IPC targets for Zen 5 and Zen 6. The new slides report that Zen 5 will be a significant architectural overhaul over Zen 4, targeting 10 to 15% IPC improvements or more. Zen 5 will also reportedly incorporate 16 core CCXs for the first time. Before we go much further, we'll need to sprinkle a healthy amount of salt on this report.
The list of improvements going into the Zen 5 core is quite extensive. The biggest gains surround the L1 cache, branch predictor, execution window, and core processing throughput. The branch predictor has received zero bubble conditional branches, high accuracy and larger BTB. Zen 5's L1 cache size has grown from 32KB on Zen 4 to 48KB now on Zen 5.
The chip's throughput has reportedly been extensively improved, featuring 2 basic block fetch units, 8 wide-dispatch/rename, 6 ALUs, 4 load and 2 store units, and more. The scheduler reportedly now has a larger structure size, and the integer scheduler is larger and more unified than previous designs. The slide also lists additional data prefetch improvements along with ISA and Security enhancements but doesn't go into any specific details.
Another considerable improvement revealed from the leaked slides is the core configuration of Zen 5's CCXs (core complexes), which have been doubled from 8 to 16. The new change marks the first time since Zen 2 that AMD has bothered to increase the core count of its CCXs, which means that we could see a 32-core "Ryzen 9 8950X" in the future.
We don't know yet what types of cores these new Zen 5 core clusters will have. Half of Zen 5's core count could be dedicated entirely to Zen 5c efficiency cores, or the entire stack could be vanilla Zen 5 performance cores. It could be a mix of both since AMD's slides suggest that there will be different models featuring FP-512 support and some models with low-power cores.
It's worth mentioning that these slides are strictly targeted toward AMD's enterprise server chips (EYPC) and aren't focused on its mainstream consumer desktop CPUs. So don't expect every detail to make its way into Ryzen 8000 chips next year, like FP-512 support. But, in general, the underlying architectural specs could make their way into Ryzen 8000.
The leaked slides also show additional projections regarding AMD's Zen 6 architecture. The slide shows that Zen 6 will have an estimated IPC target of at least 10% at the very minimum, FP16 for AI/machine learning, and a new memory profiler. Finally, the last bullet point mentions that AMD will double core counts again per CCD, jumping from 16 to 32 cores. There's a good chance this second core count doubling will include slower/more compact Zen 6 efficiency cores, but the fact that AMD could be quadrupling core counts in under three generations is impressive nonetheless.
Zen 5 is AMD's next-generation CPU architecture, expected to debut in 2024 with AMD's Ryzen 8000-series desktop and mobile chips. And remember, we must take all of this information with a heavy dose of salt, given how far away we are from an official launch.
