AMD's Zen 4 powers some of the best CPUs. The chipmaker appears to be going down the same hybrid route as Intel for the company's next-generation Ryzen 8000 (Strix Point) mobile processors based on the Zen 5 and RDNA 3.5 architectures.
In a new leak, courtesy of Performance Databases, an unidentified Strix Point chip has surfaced with the STX1-A0 silicon. It's reportedly a very early engineering sample (ES), so the retail version will likely have different specifications. Don't forget to sprinkle some salt over the Strix Point sample since it is unreleased hardware, after all.
Assuming that the HWiNFO screenshots are legit, Strix Point will reportedly leverage the 4nm process node, in all likelihood, from the Taiwanese foundry TSMC. AMD never confirmed Strix Point's manufacturing process via its notebook roadmap, only that it would leverage an "advanced node." The leaked 45W Strix Point APU reportedly has 12 Zen 5 cores with simultaneous multithreading (SMT). The distribution shows four P-cores and eight E-cores. Unlike Intel, AMD's E-cores support SMT.
Strix Point is the successor to AMD's current Ryzen 7045 (Phoenix) series, maxing out at eight cores and 16 threads. If we disregard the hybrid design for a second, Strix Point brings a 50% increase in total core count over Phoenix, assuming that AMD doesn't have a higher-core Strix Point in the works. The P-cores should be Zen 5 cores, whereas the E-cores are reportedly Zen 5c cores. The Zen 5 cores seemingly get access to 16MB of L3 cache, whereas the Zen 5c cores are constricted to 8MB of L3 cache. We're looking at 24MB of L3 cache for the Strix Point, 50% higher than Phoenix.
The 8,888 MHz base clock speed is obviously an error. The average active clock, which was 2,129.5 MHz, looks more reasonable. Remember that this is ES silicon, so the clock speeds are usually lower than the retail product. Phoenix has a maximum boost clock speed of up to 5.2 GHz, so it'll be intriguing to see how Zen 5 clocks compared to Zen 4. Another HWiNFO screenshot shows the Strix Point chip paired with 32GB of LPDDR5-6400 memory. For comparison, Phoenix embraces LPDDR5X-7500 out of the gate, but the Strix Point FP8 platform may just be using slower memory for testing purposes.
Strix Point taps into the RDNA 3.5 graphics engine. The leak reveals the processor with eight WGPs (Workgroup Processors). It's equal to 16 compute units or 1,024 stream processors. The memory on the ES silicon is clocked at 800 MHz. Phoenix has a maximum of 12 RDNA 3 compute units; therefore, Strix Point has 33% more GPU cores, not to mention the upgraded RDNA 3.5 GPU cores. Regarding clock speeds, Phoenix boasts frequencies up to 2,800 MHz. HWiNFO listed the Strix Point ES chip with 512MB of GDDR6 memory, a blatant error given that the iGPU gets its memory from the system.
Strix Point will launch in 2024 and power the next generation of gaming laptops. It's unlikely that the APUs can replace discrete graphics cards. However, the RDNA 3.5 engine should provide an acceptable level of performance for casual gamers. Meanwhile, the same combination of Zen 5 and RDNA 3.5 graphics will also be coming to the desktop AM5 socket through the Granite Ridge series. However, the iGPUs on Granite Ridge probably won't be helpful outside of basic display tasks.
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Zhiye Liu is a news editor and memory reviewer at Tom’s Hardware. Although he loves everything that’s hardware, he has a soft spot for CPUs, GPUs, and RAM.
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Rico Ismail Still using 4nm finfet? No process technology improvement from previous 7040 model?Reply
Why not Samsung 3nm GAAFET/MBCFET because TSMC 3nm FINFET is likely can't meet the performance target due to high leakage current on FINFET transistor below 4nm structure.
GCD and APU should be first in 3nm Samsung MBCFET/GAAFET four gate transistor to decrease leakage current in smaller transistor and promise higher performance and transistor density than finfet (like 3D 14nm FINFET vs 2D SOI/Silicon On Insulated on previous generation of transistor structure)
CCD must fabricated in TSMC N4X to reach 7 GHZ boost for desktop overtake the blue team (no IHS)
And 4nm for next MCD and IOD
Chaces is still using 3D stacked 7nm v-chace for cheapest prices per MB -
rluker5 I only see 8M L3 total. With Alder/Raptor the total from the P and E cores is added and placed in that line with hwinfo64.Reply
Hopefully that is another error. The chip has significant differences from Intel's and may have not been read right. -
George³
I didn't see anything useful. Notebook with PCIe X16? No way. This image is some sort of fake.rluker5 said:I only see 8M L3 total. With Alder/Raptor the total from the P and E cores is added and placed in that line with hwinfo64.
Hopefully that is another error. The chip has significant differences from Intel's and may have not been read right. -
rluker5
That could be. 780m has 32 ROPs and 48 TMUs vs this 16,64. Also I don't know about Ryzen memory downclocking, but the 800 looks like1600mhz to me and the timings are in the DDR4 range. Maybe this new chip dynamically changes timings on the fly? IDK, I've never personally messed with Ryzen mobile.George³ said:I didn't see anything useful. Notebook with PCIe X16? No way. This image is some sort of fake. -
Cooe Zen 4c/5c are NOT "E-cores"!!!! For the love of freaking god, STOP CALLING THEM THAT!!! It's literally just Zen 4 with less L3 cache & a lower peak clock-speed... That's it. They have literally NOTHING in common with Intel's entirely different architecture "E-cores"!Reply