Chinese vendor appears to be selling Arrow Lake-S engineering samples for $14
Even if they are real, there are no motherboards with compatible sockets on the market.
Chinese vendor Xianyu appears to be selling engineering samples of Intel Arrow Lake-S CPUs for just $14 online. A Sohu post citing the Arrow Lake-S CPU listing was spotted by Yuuki_AnS on X (Twitter). It looks like Xianyu managed to get a hold of "old" engineering samples Intel dumped in the trash, and is now flipping them online.
An image of the alleged engineering sample Xianyu is selling shows that, like other Intel samples, the ES chip does not state the model name — it merely says that it's a confidential chip meant for testing purposes only. The rest of the chip's labeling, however — "NA," "QDF4," and "D234..." — seems to confirm the CPU is older and was probably made over half a year ago. In fact, the image shared through the Sohu post is identical to an image harukaze5719 posted on X in August 2023.
like this pic.twitter.com/aL7HoipsCVApril 29, 2024
By now, it's almost guaranteed that Intel is using newer engineering samples that are more performant compared to samples manufactured half a year ago. Regardless, it is illegal to sell Intel engineering samples or prototypes of any kind, so there's a good chance Intel will take legal action if possible. To make matters worse, users who buy these chips won't have a motherboard to slot them into — since there are no consumer LGA 1851 socket motherboards on the market yet.
We don't know the specs of these mysterious engineering samples: we don't know how many cores they have, how high they clocks to, or how they perform. Engineering samples often get benchmarked and logged on benchmarks such as Geekbench, but this has not been the case for this chip.
Arrow Lake is the codename for Intel's next-generation desktop CPU architecture. It's a huge ordeal as it will be the first CPU architecture on the desktop side to incorporate a neural processing unit (NPU) for hardware-accelerated processing. Arrow Lake shares many similarities to Meteor Lake — including its tile-based design — but is technically a "successor" to Meteor Lake and is not just a desktop-flavored version of Meteor Lake.
Arrow Lake will sport a newer 20A process node (2nm-class), that will come with PowerVia backside power delivery technology. This alone will improve the performance/efficiency of Arrow Lake processors. AI performance is also reported to be 3x better than Meteor Lake, which will make Intel's first NPU-equipped desktop chips very competitive right off the bat. Intel's future desktop CPU lineup will also debut with the all-new LGA 1851 socket, which is expected to come with expanded I/O.
Leaks have revealed that Intel will not be changing the core count configuration of Arrow Lake processors. Intel will be producing three dies, with three distinct core configurations: 8P + 16E cores, 6P + 16E cores, and 6P + 8E cores. However, one very interesting tidbit is that Arrow Lake might not come with HyperThreading — which would make Arrow Lake the first CPU architecture in roughly 20 years to not have two threads per core.
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We will know more about Arrow Lake soon, as the new architecture is expected to debut later this year in Intel's second-generation Core Ultra CPU lineup.
Aaron Klotz is a contributing writer for Tom’s Hardware, covering news related to computer hardware such as CPUs, and graphics cards.
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DaveLTX Isn't arrow lake S going to be made on TSMC N3?Reply
These articles are just mad copy pasting -
artk2219 "which would make Arrow Lake the first INTEL CPU architecture in roughly 20 years to not have two threads per core."Reply
Depending on how you want to look at things, AMD didn't have SMT until at least Bulldozer, unless you take the view that just an integer core counts as a complete core, in which case it would be Ryzen . Personally i think integer cores count since FPU's didnt get integrated until the Pentium era, and we still call everything that came beforehand a single core CPU, and the FPU was the math co-processor, but its murky waters. -
DaveLTX said:Isn't arrow lake S going to be made on TSMC N3? These articles are just mad copy pasting
I guess they plan to make only the iGPU tile on TSMC N3 node, but the CPU tile might utilize the 20A node. The iGPU tile will be the same as Meteor Lake, leveraging the Xe-LPG architecture on a TSMC 3nm node.
But yeah, what the article mentions is wrong.
Also, it was confirmed by Intel's CEO Pat that TSMC's N3B process node would be used for the Lunar Lake GPU tiles (Lunar lake lineup which is supposed to be an ultrabook/convertible SoC succeeding Lakefield).
Also, per a recent China Times report, Intel will continue its outsourcing strategy with Arrow Lake and Lunar Lake set to leverage TSMC’s 3nm-class process nodes.
They also mention and confirm that the upcoming 15th Gen "Arrow Lake-S" lineup will utilize the Intel 20A node for the CPU tile, and TSMC’s 3nm (N3) node for the iGPU tile. And, the upgrade from Meteor to Arrow Lake will include a more advanced CPU tile (4->20A), while the iGPU tile remains unchanged.
https://www.chinatimes.com/newspapers/20240223000152-260202?chdtv
https://i.imgur.com/PotrjTz.jpeg -
Arrow Lake might not come with HyperThreading
Speaking of HT, I'm still wondering of Intel's patent which focuses on "Rentable Units" which they filed back last year. The patent calls it as “Instruction Processing Circuit“.
News went silent on this one though, so I'm not sure what to say.
https://www.freepatentsonline.com/y2023/0168898.html
IDK, if you go through the patent carefully, some details are mentioned. Here in the figure below, Intel has highlighted the difference between hyper-threading and Rentable Units on hybrid-core processors, assuming this is still in Intel's consideration for future client CPUs.
The densely shaded areas are P-cores while the lightly shaded ones represent the E-cores.
The Rentable Unit splits the first thread of incoming instructions into two partitions, assigning two different cores to each based on the complexity. There are two threads (1 and 2). The scheduler divides each into three partitions (A, B, C).
The first two partitions of 1 (1A, 1B) are executed on the P-core, while the third (1C) is handed to the E-core. Likewise, the first partition of thread 2 (2A) is processed by the E-core, while the other two (2B, 2C) are executed by the P-core.
https://i.imgur.com/h8OVtsH.jpeg
So it would appear that the Renting Unit is passing part of the work of the E-Core to the P-Core so that the second one does not find a part of the time stopped.
The patent also mentions that "Rentable Units" will use timers and counters to measure P/E core utilization and send parts of the thread to each core for processing. This inherently requires larger cache sizes, and Arrow Lake is already rumored to have 3 MB of L2 cache per core.
So basically, this appears to be a pseudo-multi-threaded solution that splits the first thread of incoming instructions into two partitions, assigning them to different cores based on complexity more like. :cautious: -
usertests The 6P + 16E die seems weird unless it's an Arrow Lake-H mobile one. It's been described as a desktop die months ago but rumors are rumors. Articles from earlier today are omitting that die:Reply
https://wccftech.com/intel-core-ultra-5-240f-arrow-lake-s-desktop-cpu-8-16-6-8-dies-entry-level-segment/
6+16 slide from January:
https://videocardz.com/newz/leaked-documents-list-intel-arrow-lake-s-with-8p16e-cores-125w-tdp-full-800-series-chipset-details -
I guess they can reuse the dies for both the Desktop and Mobile variants, if need be. But in any case, this article just copy/pasted what was previously rumored die configurations.Reply
I"m almost certain the final P+E core config is not yet finalized. Those were just rumors.
The XINO leaker seems new when it comes to rumors, and I haven't heard much from this user before though. And why would only the Ultra 5 240F come in two variants ? What about other SKUs in the lineup ?
Let me dig up some more, as I have quite a few old slides on my old backup hard drive. -
DaveLTX
It's a bit of a mess, there's also reports that Arrow Lake lower end would be based on Arrow Lake-H or whatever that only has 6+8 and would actually use 20A while the higher end cores either use TSMC N3 or Intel 3Metal Messiah. said:I guess they plan to make only the iGPU tile on TSMC N3 node, but the CPU tile might utilize the 20A node. The iGPU tile will be the same as Meteor Lake, leveraging the Xe-LPG architecture on a TSMC 3nm node.
But yeah, what the article mentions is wrong.
Also, it was confirmed by Intel's CEO Pat that TSMC's N3B process node would be used for the Lunar Lake GPU tiles (Lunar lake lineup which is supposed to be an ultrabook/convertible SoC succeeding Lakefield).
Also, per a recent China Times report, Intel will continue its outsourcing strategy with Arrow Lake and Lunar Lake set to leverage TSMC’s 3nm-class process nodes.
They also mention and confirm that the upcoming 15th Gen "Arrow Lake-S" lineup will utilize the Intel 20A node for the CPU tile, and TSMC’s 3nm (N3) node for the iGPU tile. And, the upgrade from Meteor to Arrow Lake will include a more advanced CPU tile (4->20A), while the iGPU tile remains unchanged.
https://www.chinatimes.com/newspapers/20240223000152-260202?chdtv
https://i.imgur.com/PotrjTz.jpeg
So it might sound like they have a mess trying to decide what they can *actually* use. Which might very well be the case since Intel manufacturing is a whole mess right now -
TechyIT223 Lol , 14 dollars for a CPU in itself is a huge red flag, regardless of the processor being legit to begin with.Reply
Who knows that sample even works or not. Anyway that new hyper thereading patent looks kinda interesting.
Rentable units ? -
DaveLTX
I think its a mechanical sample. How it hasn't been pointed out is beyond me...TechyIT223 said:Lol , 14 dollars for a CPU in itself is a huge red flag, regardless of the processor being legit to begin with.
Who knows that sample even works or not. Anyway that new hyper thereading patent looks kinda interesting.
Rentable units ? -
TechyIT223
It's a qualification sample. What is mechanical? You mean an engineering production unit?DaveLTX said:I think its a mechanical sample. How it hasn't been pointed out is beyond me...