The Pixel Rendering Pipelines
ATi is proud that Radeon 9700 is the first mainstream graphics chip with eight parallel pixel rendering pipelines. This is twice the amount of pipelines found in current high-end graphics chips. At a clock of 325 MHz, the eight pipelines are able to supply a fill rate of 8 * 325 = 2,600 Mpixels/s. Each pixel rendering pipeline has one texture unit, so the multi texturing fill rate is the same as the single texturing fill rate above. It might look as if one texture unit per pipeline is very little, but if you calculate the memory bandwidth requirement of eight parallel pipes with one texture unit doing a trilinear 32-bit color texture lookup, you will understand why two texture units wouldn't have made an awful lot of sense: 32 bit * 8 (trilinear filtering requires 8 texels to be read) * 8 (eight pipelines) = 2048 bit. 2048 bit would have to be read per clock, but 'only' 512 bit per clock are provided by the 256 bit-wide DDR memory interface of Radeon 9700. Bilinear filtering mode would still require 1024 bit per clock. Two texture units per pipe could never be fed by the memory interface. This is why it wouldn't have made sense to add those units.
The Pixel Shaders
Each pixel rendering pipeline of Radeon 9700 is a separate pixel shader. Following the new PS 2.0 spec, those shaders can run programs of up to 160 instructions. Each pixel shader program can do up to 32 texture sampling operations on up to 16 different texture maps and an additional 64 color operations per pass. The amount of clock cycles per pass is, of course, variable and can certainly reach rather high numbers as well, especially when anisotropic filtering is used at the same time. When the 160 instruction limitation should turn out to be too small, the result can be fed into the pixel shader for another pass without losing any precision, since the result can be handled in 64 or 128-bit floating point precision.
