Countdown To Pentium 5 Vs. Athlon 64
| Intel P4/P5 Cores | Prescott | Northwood "A" | Northwood | Willamette |
|---|---|---|---|---|
| Processor Plattform | Socket 478/Socket 775 | Socket 478 | Socket 478 | Socket 478 |
| Clock | 3.4 GHz to 5.0 GHz | 2.26 to 3.2 GHz | 1.4 to 2.6 GHz | 1.3 to 2.0 GHz |
| FSB Clock | 200 MHz | 133/200 MHz | 100 MHz | 100 MHz |
| FSB Speed | Quad-Pumped (800 MHz) | Quad-Pumped (533/800 MHz) | Quad-Pumped (400 MHz) | Quad-Pumped (400 MHz) |
| L1 Cache (Trace Cache) | 16 K µ-Ops | 12 K µ-Ops | 12 K µ-Ops | 12 K µ-Ops |
| L1 Cache (Data Cache) | 16 kB | 8 kB | 8 kB | 8 kB |
| L2 Cache (Data Cache) | 1024 kB | 512 kB | 512 kB | 256 kB |
| Circuit Density | 0.09 µm | 0.13 µm | 0.13 µm | 0.18 µm |
| Gate Length | 0.045 µm | 0.065 µm | 0.065 µm | 0.09 µm |
| CPU Die Size | ? | 146 mm2 | 146 mm2 | 217 mm2 |
| Number of Gates | ? | 55 Million | 55 Million | 42 Million |
| Gates per area | ? | 376712 gates/ mm2 | 376712 gates/ mm2 | 193548 gates/ mm2 |
| CPU Core Voltage | 1.25 Volt | 1.50 to 1.575 Volt | 1.50 Volt | 1.75 Volt |
| Current Consumption | ? | 52.7 A | 41.7 A | 43 A |
| Power Consumption (max) | 81.8 Watt | 81.8 Watt | 62.6 Watt | 75.3 Watt |
| Hyper-Threading | yes (expanded) | yes, from 2.4 GHz | no | no |
| Instruction Extensions | PNI, SSE2, SSE, MMX | SSE2, SSE, MMX | SSE2, SSE, MMX | SSE2, SSE, MMX |
The essential details of the new Pentium 5 are already known today. However, it's not completely clear if the processor with the Prescott core will be called "Pentium 5" or not. The marketing strategists at Intel are still not in agreement on this point. It would make sense to stay with this nomenclature, though, since AMD will be launching the Athlon 64 a few weeks earlier.
Basically, the Prescott core is built on Netburst architecture and is therefore based on the Northwood core. Compared to the P4, the cache sizes will be increased: the L1 data cache increases from 8 kB to 16 kB, and the L1 trace cache gets 16-K micro-operations instead of 12 K. In addition, the L2 cache is extended from 512 kB to 1 MB. With these changes, the Pentium 5 and the Athlon 64 will have equivalent L2 cache sizes.
The front side bus will remain at 200 MHz (a.k.a. 800 MHz in marketing speak), so that the bandwidth between the Northbridge and the processor is theoretically 6.4 GB/s. Data communication with the memory will run at the same speed - based on Dual DDR400. At the moment, it's still difficult to predict how successful the Athlon 64's 64 bit addressing will be in the mass market.
Rumors have it that Intel has already integrated a 64 bit extension (codenamed Yamhill) on its Prescott core, which can then be unlocked as required. This is reminiscent of the Hyper-Threading feature, which was already was integrated in the Pentium III processor hardware. In addition to the already existing command extensions such as SSE2, Prescott works with 13 new commands (PNI = Prescott New Instructions), which serve to accelerate video encoding and improve thread synchronization.
It's not just CPU-related news that we have to report: both manufacturers are working on new platforms as well, with AMD using Socket 754, and Intel, Socket 775 (Socket T, LGA construction) starting Q2 2004. Prior to that point, the Pentium 5 will make its debut on the "old" Socket 478. What's completely new about Socket 775 is the package: with the LGA (Land Grid Array) structure, the processor now no longer has pins; the electrical connection is established via half-spherical contacts, similar to the chipset components. The goal of this modification is to increase the contact surface between socket and processor, thus enabling the flow of very high electricity (100 A and more).
With regard to the manufacturing process, the Pentium 5 (Prescott) is expected to have a higher yield rate than the Northwood CPUs, so that more CPUs can be gained per wafer (300 mm diameter, 90-nanometer process). Insider experts even expect the Prescott to boast the highest yield rate out of all cores to date. In any case, for Intel this means lower production costs per individual CPU.
