|Intel CPU Roadmap Q3/98|
|Row 2 - Cell 0||Row 2 - Cell 1||Row 2 - Cell 2||Row 2 - Cell 3||Row 2 - Cell 4||Row 2 - Cell 5||Merced|
|Row 3 - Cell 0||Row 3 - Cell 1||Row 3 - Cell 2||Row 3 - Cell 3||Row 3 - Cell 4||Cascades 6xx MHz0.18 µ process133 MHz FSBw/256 kB full speed on-die L2 cache|
|Row 4 - Cell 0||Row 4 - Cell 1||Row 4 - Cell 2||Row 4 - Cell 3||Tanner 5xx MHz2 MB, 1 MB, 512 kB external full speed CSRAM L2 Cache100 (/133 ?) MHz FSBInTRo March 1999 (Intel estimate)|
|Row 5 - Cell 0||Pentium II Xeon 400-450 MHz, 2 MB, 1 MB, 512 kB external full speed CSRAM L2 Cache 400 MHz w/512 or 1024 kB L2 Cache, Launch June 29, 98450 MHz w/512tor 2048 kB L2 Cache, Launch August/September, 98|
|Row 6 - Cell 0||Row 6 - Cell 1||Row 6 - Cell 2||Row 6 - Cell 3||Row 6 - Cell 4||Coppermine 533 - 6xx MHz0.18 µ process512 kB external half speed BSRAM L2 Cache133 MHz FSB|
|Row 7 - Cell 0||Row 7 - Cell 1||Row 7 - Cell 2||Katmai 450, 500 MHz||Katmai 5xx133 FSB ?||Row 7 - Cell 5|
|Pentium II 350-400 MHz||Pentium II 350-450 MHz450 MHz Launch August 24, 98||Row 8 - Cell 2||Row 8 - Cell 3|
|Pentium II 266-333 MHz||Pentium II 266-333 MHz||Row 9 - Cell 2||Row 9 - Cell 3||Row 9 - Cell 4||Row 9 - Cell 5|
|Celeron 266 (Covington Core)||Celeron 266- 300 MHz Launch June 7, 98 (Covington Core)||Celeron 266-300 MHz, Celeron 300 'A', Celeron 333 MHz , both w/128 kB full speed on-die L2 Cache(Mendocino Core), Launch August 24, 98||Celeron 300 'A' - 366 MHz , all w/128 full speed on-die L2 Cache, 66 MHz FSB (Mendocino Core), 366 MHz Launch February 99||Celeron 300 'A' - 400 MHz , all w/128 full speed on-die L2 Cache, 66/ 100 MHz FSB (Mendocino Core)Possibly Celeron for Slot1 will be abandoned !|
|Row 11 - Cell 0||Socketed Celeron 300 'A' - 366 MHz w/128 kB cache||Socketed Celeron 300 'A' - 400 MHz w/128 kB cache|
|Pentium MMX 200-233 MHz||Row 12 - Cell 1||Row 12 - Cell 2||Row 12 - Cell 3||Row 12 - Cell 4|
|mobile Pentium II 233-266 MHz||mobile Pentium II 266-300 MHz||mobile Pentium II 266-333 MHz|
|mobile Pentium MMX 166-266 MHz||Row 14 - Cell 1||Row 14 - Cell 2||Row 14 - Cell 3|
|Row 15 - Cell 0|
|Slot M CPUs||Row 16 - Cell 1||Row 16 - Cell 2||Row 16 - Cell 3|
|Slot 2 CPUs, 100 MHz front side bus||Row 17 - Cell 1||Row 17 - Cell 2||Row 17 - Cell 3|
|Slot 1 CPUs, 100 MHz front side bus||Row 18 - Cell 1||Row 18 - Cell 2||Row 18 - Cell 3|
|Slot 1 CPUs, 66 MHz front side bus||Row 19 - Cell 1||Row 19 - Cell 2||Row 19 - Cell 3|
|New Celeron Socket, 370pins||Row 20 - Cell 1||Row 20 - Cell 2||Row 20 - Cell 3|
|Socket 7 CPUs, 66 MHz system bus||Row 21 - Cell 1||Row 21 - Cell 2||Row 21 - Cell 3|
|Mobile CPUs, 66 MHz front side bus||Row 22 - Cell 1||Row 22 - Cell 2||Row 22 - Cell 3|
The next Pentium II core at 100 MHz FSB will be Katmai , starting to ship in Q1/99, initially at 450 MHz, then soon moving to 500 MHz. Katmai will have the new MMX2 insTRuction set (old name) or 'Katmai New InsTRuctions' = KNI (pointless new name), which includes double precision floating point SIMD (single insTRuction multiple data) insTRuctions. This new insTRuction set will accelerate 3D graphics by a significant amount.
Coppermine will be a shrink of Katmai down to 0.18 µ. It will not include an on-die L2-cache, because it would otherwise interfere with Cascades. Instead of this it will continue to run with the known half speed external BSRAM L2 cache as in previous Pentium II Slot 1 CPUs. This seems more of a marketing idea rather than something that's technically necessary.
Tanner will be a Xeon with KNI, succeeding the Pentium II Xeon Slot 2 CPU, but most likely keeping its name. Tanner will include the Katmai new insTRuction set and will probably start off with 450 or 500 MHz clock speed. It will ship with 512 kB/1 MB/2 MB full speed external CSRAM L2 cache versions. I wonder what an average high speed server needs 3D enhancing insTRuctions for, but, well, I'm only a doctor and web site owner.
Cascades will not be a better, but a cheaper version of Tanner. It is a shrink of Tanner down to 0.18 µ and including a smaller 256 kB on-die L2 cache. The shrink will enable Cascades to run at 133 MHz FSB at clock speeds of more than 600 MHz.
Celeron is now available as 266 and 300 MHz version (Deschutes core), without L2 cache and running at 66 MHz FSB. On August 24 Intel will inTRoduce Celeron with 128 kB on-die L2 cache (Mendocino core ) at 300 MHz (Celeron 300 'A') and 333 MHz (Celeron 333). We can expect those Celerons with L2 cache to run almost identically as fast as a Pentium II at 66 MHz FSB (Pentium II 233 - 333) with its 512 kB half speed L2 cache. The cacheless Celeron will probably disappear at the end of 1998. The second half of 1999 will eventually bring a Celeron (Mendocino core) version that will run at 100 MHz FSB, possibly starting at 350, but certainly at 400 MHz. Before that there will be a 366/66 MHz version of Celeron released around February 1999. I expect that the socketed Celeron will be available in the same speed versions as the Slot 1 model, maybe the Slot 1 Celeron will even disappear, barring a convenient upgrade path to the new Pentium II with KNI (Katmai).
The Pentium II (Klamath/Deschutes core) we have now will soon disappear. The Celeron with on-die L2 cache will first make the 66 FSB versions of the Pentium II obsolete (Pentium II 233-333), so that those will be gone by the end of 1998 or latest by the first quarter 1999. As soon as Intel starts selling Celeron at 100 MHz FSB, the Pentium II (Deschutes core!!!) at 350 and 400 MHz will become obsolete too. At this time Pentium II CPUs with Katmai core , including the new insTRuctions called KNI or previously MMX2 will be out, replacing the Pentium II CPUs with Deschutes core. As you can see, at this time the difference between Pentium II and Celeron will mainly be determined by the Celeron's lack of MMX2 or KNI as well as the top speed difference of 400 MHz for Celeron and 500 MHz for Pentium II (Katmai). This means that applications that do not use MMX2/KNI will run virtually as fast on Celeron as on a Pentium II/Katmai at the same clock speed.
The socketed Celeron will be launched in Q1/99. The idea behind this different package is nothing else but cost reduction . Slot 1 is way too expensive and too sophisticated for a solution that's as plain as the Celeron (Mendocino core with 128 kB L2 cache on die). The socket will contain 370 pins and will NOT be in any way compatible to Socket 7, which is easy to comprehend when you realize that Celeron has got the L2 cache already in the package and it's using the P6 (GTL+ protocol) instead of the Pentium bus.
Merced is not supposed to launch before 2000 now, using a new slot called 'Slot M'. A few Merced IA64 tidbits are its 'explicit parallelism', which results in several parallel machine codes after compilation of the source code. This baby runs under the name 'EPIC' for 'explicit parallel insTRuction computing'. Merced will offer 128 integer and 128 floating point registers and multiple integer and floating point units, which can all work in parallel. Intel calls this 'massive hardware resources'. IA32 is only capable of 'implicit' parallelism, resulting in one machine code after compilation. IA32 offers only 8-32 integer and 8-32 floating point registers and has only got 'few' integer and floating point units, if I'm not mistaken 'few' is an actual 'two'.
Aren't You Confused Yet?
Intel and its naming policy in combination with its new segmentation idea can easily confuse every user out there. We should realize that there is a serious difference between code names and product names. The Pentium II as well as the Celeron are the typical example, the Pentium II Xeon will go in the same direction.
Let me get into the Pentium II issue first.
When Pentium II was released, the used core had the code name 'Klamath '. This stood for a core which was a development of the Pentium Pro core and manufactured at 0.35 µ process. This Klamath core was always used together with 512 kB external L2 cache, placed into the Pentium II carTRidge and sold in versions of 233 - 300 MHz. As a matter of fact, the 233 - 300 MHz Pentium II CPUs available now are still using the 0.35 µ Klamath core. We can also say that the Klamath core is the 'oldest' Pentium II core.
Next came the 'Deschutes ' core. Deschutes was nothing else but a shrink of Klamath down to 0.25 µ. This means this chip did/does not have any new features over Klamath. Now unfortunately the Deschutes core is used in several different Intel CPU lines, and here is where the confusion starts. For the Pentium II, Deschutes is used in the 333, the 350 and 400 MHz version, again in combination with 512 kB external half speed L2 cache. You can indeed find a new feature in those CPUs, although it is not determined by the CPU core. Those later Pentium II CPUs can handle more than 512 MB of memory, due to a new tag RAM chip in the carTRidge.
The name Pentium II will continue, maybe with a little addition though, when the new 'Katmai ' core will be placed into the carTRidge. Katmai has indeed new features, carrying the highly sensible name 'Katmai New InsTRuctions' or 'KNI'. Imagine a car manufacturer would call the new features of its car 'the new features'. Those wonderful KNI will mainly improve 3D gaming and some 3D modeling possibly as well. Katmai will be the third core used in a Pentium II processor, maybe called 'Pentium II plus' or something like this (I guess Intel is working hard on this new name as well).
Coppermine (short 'CuMine') will finally be CPU core number four used in the Pentium II product line, a shrink of Katmai to 0.18 µ. It will only improve the clock speed over Katmai, there are no new features expected. However, if Katmai and Tanner are indeed going to be significantly different, it would make sense to include on-die L2 cache on Coppermine, because it would not interfere with Cascades.
This CPU, praised by me for its good price/gaming performance ratio, but ripped apart from many (conservative or old fashioned?) editors around the globe has shown to be Intel's most conTRoversial product. For me the fact is there, Celeron is a good processor and going on about its office performance bores me to death. Celeron is also using the 0.25 µ Deschutes core, however right now without any L2 cache, crippling its office performance quite a bit. It also was casTRated from the Pentium II's SMP (dual CPU) abilities. The latter will continue to be TRue for Celeron, the L2 cache story is about to change ...
Now there is a breeze of fresh air forcefully blowing into the Celeron family. Celeron will get its L2 cache! This L2 cache is not outside the CPU core as in case of the Pentium II, it's 'on-die' and it's running at CPU clock, not at only half the CPU clock as in Pentium II CPUs. 'On-die' means that the L2 cache is on the same piece of silicon as the CPU core, thus the new chip is different from Deschutes and needs a new code name. This new code name is 'Mendocino '. The L2 cache size is only 128 kB, but running faster than in a Pentium II. It changes the performance story for the new Celeron products, the Celeron 300 'A' and the Celeron 333 significantly. With its L2 cache back, the Celeron will perform a lot better than without the L2 cache, as a matter of fact it will get dangerously close to Pentium II performance. Although the CPU will look pretty much the same as the known Celeron, the performance will blow away all those above mentioned editors. This raises the question if Intel is a bit crazy. Celeron has an, admittedly unjustified, bad name for many people in the market. Using the same name for a new and vastly improved product doesn't seem very wise to me. Intel can only hope that the users out there will read some well informed publications and that those lame editors will get the message in the first place.
Intel's road map doesn't show anything about KNI being inTRoduced into the Celeron family for the next time. This will be the major difference to Pentium II ('plus'?) when Katmai is out, not the office application performance anymore. The new Celeron will make the Deschutes Pentium II disappear pretty soon though.
Pentium II Xeon
Oh my dear, what a painful long name!! Intel must really have ran out of ideas when naming the new workstation/server CPU! Xeon is also using the Deschutes core, so here's product line number 3 that uses it. Again, there's mainly a difference in L2 cache, Xeon has bigger full speed L2 caches, of advantage for servers or SMP workstations. Xeon can also address more memory and can run in more than just dual CPU configuration.
The next Pentium II Xeon (Pentium II Xeon 'A' maybe?) will be equipped with 'Tanner '. Tanner is obviously different to Katmai, so here's where the ways of Pentium II and Pentium II Xeon will part. All we know now about Tanner is that it will include KNI. So does Katmai, which makes it obvious that we have to expect a difference elsewhere between the two cores. Tanner may be able to run at 133 MHz FSB already.
Cascades will not only be a shrink of Tanner down to 0.18 µ, but it will also include 256kB full speed on-die L2 cache. This will make it an 'el cheapo'-Tanner, the 'Celeron for Advanced Users' if you allow. It will be interesting for workstations, which don't need as much L2 cache, but can use the 133 MHz FSB and a higher CPU core speed (over 600 MHz). Servers will run better with the larger L2 cache of Tanner.
New Slot 1 'SECC2' Form Factor
The Pentium II carTRidge will soon look different, the so called 'T-plate', which built the back of the CPU where the heat sink was fixed will be removed, so that the heat sink will be attached directly to the chips. This will of course reduce cost and we will get a half naked Pentium II.
|Intel CPU Pricing Roadmap Q3/98|
|From||April 15, 1998||June 7, 1998||July 26, 1998||August 24, 1998||October 25, 1998||Tanner Launch|
|Pentium II Xeon (?) Code Name Tanner500 MHz w/512 kB L2 Cache||n/a||n/a||n/a||n/a||n/a||$931|
|Pentium II Xeon 450 MHz with 2 MB L2 Cache||n/a||n/a||$3,680||$3,690||$3,690||$3,690|
|Pentium II Xeon 450 MHz with 1 MB L2 Cache||n/a||n/a||$2,680||$2,680||$1,980||$1,980|
|Pentium II Xeon 450 MHz with 512 kB L2 Cache||n/a||n/a||$1,060||$1,060||$820||$820|
|Pentium II Xeon 400 MHz with 1 MB L2 Cache||n/a||n/a||$2,840||$ 2,840||$1,980||$1,980|
|Pentium II Xeon 400 MHz with 512 kB L2 Cache||n/a||n/a||$1,120||$1,120||$820||$820|
|From||April 15, 1998||June 7, 1998||July 26, 1998||August 24, 1998||October 25, 1998||Row 8 - Cell 6|
|Pentium Pro 200 MHz with 1 MB L2 Cache||$2,700||$2,700||$2,700||n/a ?||n/a ?||Row 9 - Cell 6|
|Pentium Pro 200 MHz with 512 kB L2 Cache||$1,050||$1,050||$1,050||n/a ?||n/a ?||Row 10 - Cell 6|
|Pentium Pro 166 MHz with 512 kB L2 Cache||$412||$412||$412||n/a ?||n/a ?||Row 11 - Cell 6|
|From||April 15, 1998||June 7, 1998||July 26, 1998||August 24, 1998||October 25, 1998||Katmai Launch|
|Pentium II(?)Code Name Katmai500 MHz||n/a||n/a||n/a||n/a||n/a||$820|
|Pentium II(?)Code Name Katmai450 MHz||n/a||n/a||n/a||n/a||n/a||$580|
|Pentium II 450 MHz||n/a||n/a||$670||$670||$560||$520|
|Pentium II 400 MHz||$830||$720||$590||$590||$380||$320|
|Pentium II 350 MHz||$630||$520||$420||$420||$210||$190|
|Pentium II 333 MHz||$500||$410||$320||$320||$180||$180|
|Pentium II 300 MHz||$380||$310||$210||$210||$190||n/a ?|
|Pentium II 266 MHz||$250||$200||$160||$160||n/a ?||n/a ?|
|Pentium II 233 MHz||$200||$160||$160||$160||n/a ?||n/a?|
|From||April 15, 1998||June 7, 1998||July 26, 1998||August 24, 1998||October 25, 1998||Celeron 366 MHz Launch|
|Celeron 366 MHz with 128 kB on-die L2 Cache||n/a||n/a||n/a||n/a||n/a||$190|
|Celeron 333 MHz with 128 kB on-die L2 Cache||n/a||n/a||n/a||$192||$160||$150|
|Celeron 300 MHz with 128 kB on-die L2 Cache"Celeron 300 'A'"||n/a||n/a||n/a||$150||$140||$110|
|Celeron 300 MHz||n/a||$160||$160||$110||$90||$90|
|Celeron 266 MHz||$160||$110||$110||$90||$90||n/a|
|From||April 15, 1998||June 7, 1998||July 26, 1998||August 24, 1998||October 25, 1998||Row 28 - Cell 6|
|Pentium MMX 233 MHz||$140||$140||$110||$110||n/a||Row 29 - Cell 6|
|Pentium MMX 200 MHz||$95||$95||$95||$95||n/a||Row 30 - Cell 6|
I think that there isn't much to say about the pricing roadmap. The only interesting thing are the asTRonomical prices of the upcoming Xeon CPU.
This is the according roadmap of Intel's chipset plans.
|Intel Chipset Roadmap Q3/98|
|Row 2 - Cell 0||Row 2 - Cell 1||Row 2 - Cell 2||Row 2 - Cell 3||Row 2 - Cell 4||Carmel100 MHz FSB for quad SMP133 MHz FSB for dual SMP8 GB supportPCI 64/66 supportUlTRa DMA/66 support|
|Row 3 - Cell 0||Row 3 - Cell 1||450NX|
|Row 4 - Cell 0||440GX||Row 4 - Cell 2||Row 4 - Cell 3|
|Row 5 - Cell 0||Row 5 - Cell 1||Row 5 - Cell 2||Row 5 - Cell 3||Camino (Intel 820)RAMbus support100/133 FSBAGP 4x1 GB supportUlTRa DMA/66 support|
|440BX||Row 6 - Cell 1|
|440LX||Row 7 - Cell 1||Row 7 - Cell 2|
|Row 8 - Cell 0||Row 8 - Cell 1||Row 8 - Cell 2||Row 8 - Cell 3||Whitney (Intel 810) 66/100 MHz FSBdesigned for socketed (!!) Celeron|
|Row 9 - Cell 0||Row 9 - Cell 1||Row 9 - Cell 2||440ZX 66 MHz FSB|
|Row 10 - Cell 0||Row 10 - Cell 1||Row 10 - Cell 2||Row 10 - Cell 3||440ZX 100 MHz FSB|
|440EX||Row 11 - Cell 1||Row 11 - Cell 2|
|430TX||Row 12 - Cell 1||Row 12 - Cell 2||Row 12 - Cell 3||Row 12 - Cell 4||Row 12 - Cell 5|