Rambus is a very hot topic. Intel has been promoting Rambus as the new memory standard since late 1996. Now, eighteen months later a few DRAM manufacturers have prototype silicon in hand. Because it uses a completely new interface, Rambus requires a whole new generation of chip sets. Intel's Rambus platform is targeted for mid 1999 using the Katmai processor. Because of the risks associated with Rambus, we also expect that Intel will offer a Katmai platform using a BX-like chip set supporting SDRAM at the same time.
Isn't Rambus going to be really fast?
Remember, there are two kinds of fast - low latency and high bandwidth. Rambus offers extremely high bandwidth, but has slower latency than even standard SDRAM. Its slower latency will compromise CPU performance, but its higher bandwidth exceeds the ability of the CPU to use. This does not translate to "fast".
Doesn't Rambus run at 800 MHz?
It is described as 800 MHz DRAM, but the bus actually runs at a 400 MHz clock with a double data rate approach like AGP and DDR SDRAM. In order to hit this clock speed, the bus width had to be reduced by 75%. At 16 bits wide, it is not wide enough to issue commands to the DRAM in the standard manner. It must packetize and serialize the commands and data between the controller and the DRAM chip. This adds delays in the path between the chip set and DRAM, resulting in slower access latency.
What is "Fake Rambus"?
Because of the uncertainty of Rambus, Intel is developing a version of the Rambus Memory Module that doesn't use Rambus DRAM at all. It uses SDRAM. This type of module may be cheaper and easier to get than "Real Rambus", but its performance will be even worse than Rambus. Each module will have an additional translator chip that increases latency further, making fake Rambus probably the slowest high speed memory on Earth. Intel may even use "Fake Rambus" to demonstrate how Rambus is faster than SDRAM. Don't fall for it.
Can ultra high bandwidth make up for poor latency?
Not really. Apply a little psychology to the question. First, mess up by being slow to deliver what the CPU requires, then try to make up for it by offering the CPU data that it may not be able to use - faster than it can accept it. Sounds like something men do when they forget their anniversary or wife's birthday. It doesn't work in relationships, or in PC architecture.
If you read the article "Bandwidth vs. Latency " posted here a few weeks ago, you may recall a chart that shows how the performance profile of the CPU, peak burst bandwidth and DRAM latency have progressively been getting out of balance. The Katmai/Rambus platform of 1999 is even worse in this respect. Intel seems to prefer to fix the part that is not broken, while further degrading the performance attributes that most desperately need attention.
For the full context of this analysis please see the article "Bandwidth vs. Latency ".
This article will focus almost entirely on Rambus performance issues. But, there are several other barriers that the OEM and user will face if they choose to adopt Rambus. We should expect Rambus to be rather expensive. It has a large die and a new and expensive packaging technology. It burns a lot of power and introduces new challenges regarding cooling and power management. For the first six months of its life, Rambus platforms will not be able to support a memory capacity of more than 256 MB. This seems more like the minimum configuration for a 500 MHz Katmai platform, not the maximum. These and other issues will be covered in future articles. For now, lets dive in to the performance analysis.