Intel Runs On Complex Cycles
Before we talk about Keifer we will look at Intel's processor development cycle to get a better understanding of how the CPU chess board is laid out. Many of the upcoming products can be anticipated by knowing their projected time frame and keeping track on Intel's manufacturing technologies. Building a processor factory (these are called fabs) tears a multi-billion dollar hole in a semiconductor company's budget, which is why they need to make sure that the intended products will be profitable. Over time, Intel has come up with a highly efficient cycle that it seems to be applying now:
1
Deploy a new manufacturing process in an odd year (e.g. 65 nm in 2005) and update or shrink the current products (Pentium 4, Pentium D) to maximize yield rates for the upcoming product generation as early as possible. Launching mobile processors first is also beneficial, as these do not require highest clock speeds.
Example: The 65 nm process was introduced in 2005 and first powered the Pentium 4 6x1 and Pentium D 900 processors. The Pentium M has always adopted new manufacturing technologies first (90 nm Dothan, 65 nm Yonah).
2
Deploy a powerful new processor in the following, even year (e.g. Core 2 in 2006). This new CPU implements the latest micro-architecture and a balanced mix of an ideal core count, features and clock speed, so it reaches the goals for performance and performance per Watt based on current fabrication.
Example: Core 2 launches July 27.
3
Derive low-cost products from the current single-die to maximize yields and profit. A partly defective Core 2 dual core processor may still be sold as a cache reduced-version (Allendale) or a single-core model (Millville) - depending on where the defects are located.
Example:Core 2 Duo E6400, E6300, E4200 (2 MB L2 cache only), a Single core Core 2 will follow (possibly as Celeron).
4
This step only applies for the multi core generation: Create a next-generation product by merging two current single-die processors into one processor package. Clock speed might have to be reduced to stay within the given thermal envelope, but this offers a cost-effective way of doubling the core count.
Example: Pentium D Presler is based on two Pentium 4 Cedar Mill dies, Core 2 Kentsfield will be based on two Core 2 Duo Conroe dies.
5
At this point, the existing product(s) should be ready to be adjusted to the next-generation manufacturing process (45 nm in 2007). Clock speed can be adjusted according to progress in manufacturing.
Example: 45 nm will be introduced in 2007.
Depending on how well this machine is oiled, the cycle may be somewhat larger or shorter than two years. Having this principle in mind, it is logical that the first physical quad core processor, Harpertown, will arrive in 2008. For the time being, refinements in the 65 nm process should allow for adjusted Conroe and Kentsfield clock speeds at unchanged energy consumption within the given thermal envelope specifications. Harpertown will also be the basis for the eight core Gainstown that could follow after few months.
