Rambus And Future Plans
Rambus increases peak burst bandwidth to a level that is hard to take advantage of in 1998 and 1999 desktop PCs. At 100 MHz and 133 MHz SDRAM can satisfy the CPU's bandwidth requirement. But in the year 2000, Intel may drive the CPU bus speed to 200 MHz, skipping 150 or 166 MHz. DDR SDRAM can match the CPU's bandwidth at this speed, but ordinary SDRAM probably could not. Obviously, such a CPU bus speed strategy would favor Rambus.
Beyond just CPU bus speed, there are other factors that will favor high bandwidth on other platforms. One example is multiprocessor servers. Pentium II processors are able to address up to four CPUs per bus. In order to implement an 8 CPU multiprocessor server, the chip set must support two CPU buses. Even at 100 MHz, these two buses can combine to demand the equivalent of a single 200 MHz bus (1.6 GB/s). Rambus seems well suited to this requirement, but there are barriers relating to power dissipation and maximum system DRAM capacity (described in more detail below).
Also, in the evolution of Intel's product line, microprocessor architectures are being optimized to better tolerate increasing latencies. In the P6 generation, speculative execution helps to offset latency problems, and explicit data prefetch instructions will be introduced in Katmai that will pre-load the cache - effectively increasing its hit rate. Jumping ahead to Merced, explicit parallelism can reduce or eliminate the occurrence of mispredicted branch instructions in the CPU core. This also has the effect of isolating the CPU from DRAM latency, but it will require a shift to new IA64 VLIW style applications code. This transition will not happen rapidly in the mainstream desktop market.
On the other hand, some types of mainstream X86 applications are not very susceptible to DRAM latency. One good example is highly redundant floating point code using data sets that are small enough to fit in the L1 or L2 cache. Some games and 3D benchmarks fit into this category. However, as games further evolve they will use more sophisticated game logic code, environmental modeling, larger floating point data sets that exceed the cache size, and more challenging multimedia functions that run concurrently. These factors will combine to demand better latencies as well as higher bandwidth.
