SRAM scaling isn't dead after all — TSMC's 2nm process tech claims major improvements

TSMC
(Image credit: TSMC)

SRAM scaling came to a screeching halt with the last round of new process nodes, portending a dark future where on-chip memories would become increasingly expensive. However, contrary to what we've seen in the past, SRAM scaling apparently isn't dead after all. 

TSMC has announced that its N2 process technology (2nm-class) offers substantial improvements in performance, power efficiency, and area (PPA) compared to previous-generation nodes. However, there is one more thing that TSMC hasn't yet publicly discussed: considerably smaller SRAM cells and higher SRAM density (38 Mb/mm^2), which will have an impact on the costs and performance of next-generation CPUs, GPUs, and system-on-chips.  

TSMC's upcoming N2 node will debut with gate-all-around (GAA) nanosheet transistors, promising a significant power reduction and a boost in performance and transistor density. Compared to the N3E fabrication technology, chips built on N2 are expected to reduce power usage by 25% to 30% (at equivalent transistor count and frequency), boost performance by 10% to 15% (with the same transistor count and power), and achieve a 15% increase in transistor density (maintaining the same speed and power). 

But a noteworthy aspect of TSMC's N2 is that this production node also shrinks HD SRAM bit cell size to around 0.0175 µm^2 (enabling SRAM density of 38 Mb/mm^2), down from 0.021 µm^2 in the case of N3 and N5, according to a paper that TSMC will present at the upcoming IEDM conference this December. 

Swipe to scroll horizontally
Row 0 - Cell 0 N3 vs N5N3E vs N3N3P vs N3EN3X vs N3PN2 vs N3EN2P vs N3EN2P vs N2A16 vs N2P
Power-25% ~ -30%-34%-5% ~ -10%-7%***-25% ~ -30%-30% ~ -40% -5% ~ -10%-15% ~ -20%
Performance+10 ~ +15%+18%+5%+5% Fmax @ 1.2V**+10% ~ +15%+15% ~ 20%+5% ~ +10%+8% ~ 10%
Density*?1.3X1.04X1.10X***1.15X1.15X?1.07X ~ 1.10X
SRAM Density33.55 Mb/mm^231.8 Mb/mm^2??38 Mb/mm^2???
SRAM Cell Size0.0199 µm^20.021 µm^2??0.0175 µm^2???
HVMQ4 2022Q4 2023H2 2024H2 2025H2 2025H2 2026H2 2026H2 2026

This is a major breakthrough as SRAM has become particularly hard to scale in recent years. For example, TSMC's N3B (1st Generation 3nm-class technology) provided little advantage over N5 (a 5nm-class node) in this regard, while the HD SRAM bit cell size of N3E (2nd Generation 3nm process) is 0.021 µm^2 and offers no advantages in terms of SRAM scaling compared to N5. With N2, TSMC has managed to finally shrink HD SRAM bit cell size and, therefore, increase SRAM density. 

TSMC's GAA nanosheet transistors appear to be the main enabler of smaller HD SRAM bit cell sizes. GAA transistors offer improved electrostatic control over the channel by completely surrounding it with the gate material, which helps reduce leakage and allows transistors to scale down in size while maintaining performance. This enables better scaling of transistor dimensions, which is crucial for reducing the size of individual components like SRAM cells. Also, GAA structures allow for more precise threshold voltage tuning, which is essential for the reliable operation of transistors overall, and SRAM cells in particular, making it possible to further shrink their sizes. 

Modern CPU, GPU, and SoC designs are very SRAM-intensive as these processors rely heavily on SRAM for numerous caches to handle large amounts of data efficiently. Accessing data from memory is both performance-draining and power-intensive, making ample SRAM crucial for optimal performance. Looking ahead, demand for caches and SRAM is set to keep growing, so TSMC's achievement with SRAM cell size represents a very important one. 

Earlier this year, TSMC said that N2's gate-all-around nanosheet transistors were delivering over 90% of their target performance, and yields for 256 Mb (32 MB) SRAM devices were surpassing 80% in certain batches. As of March 2024, the average yield for 256 Mb SRAM had reached approximately 70%, up significantly from around 35% in April 2023. Device performance has also shown steady improvement, with higher frequencies achieved without increasing power consumption.

Anton Shilov
Contributing Writer

Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.

  • Pierce2623
    If true, this is legitimately awesome news. I really thought SRAM scaling would continue to be in a really bad place which meant newer chips had much less possibility for downsizing since ~90% of a consumer CPU is SRAM.
    Reply
  • tennis2
    chips built on N2 are expected to reduce power usage by 25% to 30% (at equivalent transistor count and frequency), boost performance by 10% to 15% (with the same transistor count and power), and achieve a 15% increase in transistor density (maintaining the same speed and power).

    These should be OR statements please.
    Reply
  • usertests
    There are mistakes in the table. I'll leave it to you to figure out what they are.
    Reply
  • 80251
    Would this make any difference to AMD's 3D V-Cache? Or is that a different technology from SRAM?
    Reply
  • bit_user
    Pierce2623 said:
    ~90% of a consumer CPU is SRAM.
    Absolutely not. Where did you ever find such a figure?
    Reply
  • Steve Nord_
    Admin said:
    TSMC's N2 fabrication process shrinks SRAM bit cell size, increases SRAM density to ~38 Mb/mm^2.
    Get those soft error hardness tests at 62-68°C prepped. (Will TPUs get through post-quantum auth?)
    Reply
  • Pemalite
    Having to scroll horizontally on a table is ridiculous when the table is only using 20% of my displays horizontal real estate.
    You know you can optimize a website for mobile without sacrificing desktop usability? You can resize things for different displays.
    Reply
  • bit_user
    Pemalite said:
    Having to scroll horizontally on a table is ridiculous when the table is only using 20% of my displays horizontal real estate.
    You know you can optimize a website for mobile without sacrificing desktop usability? You can resize things for different displays.
    The authors who write the articles aren't the ones that control the layout, sadly. The publisher controls this, and it's the same across virtually all of their sites.

    That said, I do think perhaps it would've worked better for the author to transpose the table. It's 6x8 (HxW), so it would've resulted in less scrolling to do that. More importantly, you're usually wanting to see how the nodes compare on a per-metric basis, which you could do without scrolling if it were transposed.
    Reply
  • Pierce2623
    bit_user said:
    Absolutely not. Where did you ever find such a figure?
    Not sure what happened there. It was supposed to be 30% and even that is a little high. Keep in mind I’m not referring only to cache but all the storage in all the various buffers and registers too.
    Reply
  • bit_user
    Pierce2623 said:
    Not sure what happened there. It was supposed to be 30% and even that is a little high. Keep in mind I’m not referring only to cache but all the storage in all the various buffers and registers too.
    Huh. Yeah, 30% sounds more reasonable.
    Reply