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AMD Preps for Zen 4: Different Types of Cores Now Supported in Linux

AMD EPYC Processor
(Image credit: AMD)

Tech sleuths are following AMD as it prepares its new Zen 4-based architecture. As the prepares its next-gen CPU, some eagle-eyed individuals have found details about the next-gen parts on Linux and other platforms.

AMD has quietly uploaded temperature sensor driver support for Zen 4 and Zen 4C cores, reports Phoronix. While these two cores share the same microarchitecture, they are different and will power AMD's 96-core Genoa and 128-core Bergamo processors, respectively, so it is not surprising to see separate drivers. The CPUs are marked as AMD Family 19h Models 10h-1Fh and A0h-AFh. 

Perhaps, a more intriguing innovation is a new Scalable Machine Check Architecture (SMCA) of some future AMD platforms that could use different types of SMCA and therefore cores. 

"Future AMD systems will have different bank type layouts between logical CPUs," wrote Yazen Ghannam, an AMD engineer. "So having a single system-wide cache of the layout won't be correct. […] Patch 1 adds new bank types and error descriptions used in future AMD systems. Patch 2 adjusts how SMCA bank information is cached." 

So far, AMD has not announced a single hybrid processor that integrates different types of cores, though the company has never completely excluded such a possibility. Since AMD will have Zen 4 and Zen 4C cores next year, perhaps this is the time when the company might consider a CPU with both big and smaller cores. Alternatively, a new SMCA may indicate that Zen 4C will have a different machine check architecture than other Zen cores, which is why AMD needs to implement its support into Linux. 

In any case, both the new temperature sensor drivers and SMCA implementation indicate that preparations for AMD's Zen 4-series cores are in full swing. 

Anton Shilov
Anton Shilov

Anton Shilov is a Freelance News Writer at Tom’s Hardware US. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.

  • $h0nuff
    Pretty sure this confirms what we already know. 2 types of Zen4 core ccd parts. Those with 3D cache and those without.

    Changes to error correction to address the higher cache parts makes sense.

    Changes to drivers and/or updated die temp sensor location makes sense with 3DV parts.

    Nothing I see points to anything beyond that. Not sure about server parts but based on the preso and brief look at the transistor changes on the package, the desktop plan is different.

    "..Two types of cores in one.." or something along those lines. They're going to modify power and clocks on-the-fly in conjunction with an updated scheduler.
    Reply
  • TJ Hooker
    $h0nuff said:
    Pretty sure this confirms what we already know. 2 types of Zen4 core ccd parts. Those with 3D cache and those without.

    Changes to error correction to address the higher cache parts makes sense.

    Changes to drivers and/or updated die temp sensor location makes sense with 3DV parts.

    Nothing I see points to anything beyond that. Not sure about server parts but based on the preso and brief look at the transistor changes on the package, the desktop plan is different.

    "..Two types of cores in one.." or something along those lines. They're going to modify power and clocks on-the-fly in conjunction with an updated scheduler.
    Zen 4 vs 4c has nothing to do with 3D cache as far as I'm aware. AMD describes Zen 4c as being optimized for power efficiency and density, so roughly analogous to "little" cores like Gracemont cores in Alder Lake.
    Reply
  • $h0nuff
    TJ Hooker said:
    Zen 4 vs 4c has nothing to do with 3D cache as far as I'm aware. AMD describes Zen 4c as being optimized for power efficiency and density, so roughly analogous to "little" cores like Gracemont cores in Alder Lake.

    I respectfully disagree..

    4c is "cloud enhanced". Of course they haven't yet provided the deets but I read that to be designed for specific, repetitive tasks requiring less clock and power per thread.

    "Density optimized cache" ie..stacked and power enhancements are stated as 4c features but who knows..

    They don't have a big/small, big/little, big/bigger arrangement taped yet and we won't see it in Zen4, 4c, 4xxx.

    They are, quite simply, using an updated scheduler and fancy up or down-clocking to execute threads more efficiently. Pretty slick as an interim response to Intel plans.
    Reply
  • TJ Hooker
    $h0nuff said:
    I respectfully disagree..

    4c is "cloud enhanced". Of course they haven't yet provided the deets but I read that to be designed for specific, repetitive tasks requiring less clock and power per thread.

    "Density optimized cache" ie..stacked and power enhancements are stated as 4c features but who knows..

    They don't have a big/small, big/little, big/bigger arrangement taped yet and we won't see it in Zen4, 4c, 4xxx.

    They are, quite simply, using an updated scheduler and fancy up or down-clocking to execute threads more efficiently. Pretty slick as an interim response to Intel plans.
    So you think Zen 4c will have 3D cache and Zen 4 won't, or vice versa? Where have you seen AMD mention "density optimized cache" with respect to Zen 4c?
    AMD specifically says "tuning the core design for density and increased power efficiency to enable higher core count processors with breakthrough performance per-socket." Adding 3D cache wouldn't do anything to improve core density on its own.
    https://www.amd.com/en/press-releases/2021-11-08-amd-unveils-workload-tailored-innovations-and-products-the-accelerated
    Reply