iBuypower's $5,500 Ultra Gaming System
Features
By
Darren E. Polkowski
Published
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Memory Timings
The iBuyPower system used 2 GB of Corsair CM2X1024 - 6400 memory at the default settings specified by the SPD.
While memory timings aren’t as major a factor in system performance today as they were 5 or 10 years ago, these settings will still yield more system performance if configured correctly. Once again, the iBuyPower system just takes the default values from the modules’ internal serial presence detect (SPD) chip, failing to cash in on simple system optimization opportunities.
The table below describes the various memory timings and compares the values used by the iBuyPower and two other systems.
Swipe to scroll horizontally
| Memory Timing | iBuyPower | Falcon-NW | Biohazard | Explanation of the Timing | |
|---|---|---|---|---|---|
| tCL | CAS Latency | Auto (5) | 4 | 5 | Delay between the CAS signal and the availability of valid data on the data pins (DQ). |
| tRCD | RAS to CAS Delay | Auto (5) | 4 | 4 | Delay before a read/write command after bank activation. The cells need to be stabilized by sense amplifiers for proper operation. |
| tRP | RAS Precharge (Row to Row) | Auto (5) | 4 | 4 | Time delay needed to close one row access and open a new one. |
| tRAS | RAS Active to Precharge Delay | Auto (18) | 15 | 14 | Minimum RAS activation time delay, or the time from the bank activate command until the precharge command can be executed. |
| CMD | Chip Select Issue Delay (Command Rate) | Auto (2) | 2 | 2 | Time needed between the chip select signal and when commands can be issued to the RAM module IC. |
| tRRD | RAS to RAS Delay (Between Banks) | Auto (3) | 4 | 5 | Row to Row delay from a bank to one on another active bank. |
| tRC | RAS to RAS Delay - Bank Cycle Time (Same Bank) | Auto (22) | 13 | 34 | Row to Row delay on the same bank. One row discharges and another is activated. (Minimum time of tRAS = tRP). |
| tWR | Write Recovery Time | Auto (5) | 4 | 6 | Delay between writes to ensure proper writing to the cells. Ideally tRAS minus tRCD to ensure a premature RAS precharge does not wipe out the data. |
| tWTR | Write to Read Delay | Auto (9) | 9 | 11 | The delay to prep the bus for read after a write (turn on or off the appropriate I/O buffers, clear existing data, etc.) |
| tREF | DRAM Auto-Refresh Rate | Auto (7.8) | 7.8 | 7.8 | Rate at which the DRAM’s charge is refreshed in microseconds. Prevents corruption by sending data to sense amplifiers and back to the refreshed cell. |
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