Discrepancy: Marketing, Yield, Artificial Castration
From the beginning, Intel put safety precautions into place that would ensure that the board manufacturers couldn't easily activate the fast memory access (PAT) with the less expensive 865 chipset. The price difference with the chipset alone is at least $16, which results in a difference of up to $55 per board for the end user.
As a result of Asus working directly with THG, the company decided to take the difficult step of giving us exclusive and exciting information about how PAT can be reactivated with the 865/Springdale chipset. This information will also help to take care of any possible misunderstandings among hardware enthusiasts.
And now the details. With the 875P chipset (Canterwood), PAT is only activated when a CPU with FSB 800 is detected by the Northbridge of the chipset. This involves the signal BSEL [1:0]. The following states are shown in the table below:
| BSEL1 | BSEL0 | CPU Freq |
|---|---|---|
| 0 | 0 | FSB400 |
| 0 | 1 | FSB533 |
| 1 | 0 | FSB800 |
| 1 | 1 | Reserved |
With the 875P chipset, PAT is only switched on when the signals are BSEL1=3D1 and BSEL0=3D0 ("FSB800"). However, this function is deactivated with the 865 chipset (Springdale). Asus found a sort of "back door" for this. Although the state [1:0] is blocked on the 865 chipset (Springdale), Asus still discovered that the fast memory access PAT is kept open for the states [0:0] and [0:1], or FSB 400 and FSB 533, respectively.
Because the BSEL signals are normally used for controlling the clock generator as well, Asus came up with a trick: with the help of the Super I/O unit, which is integrated on all boards of the P4P800 series, the BSEL signals are intercepted and manipulated. This allows the clock generator to be programmed with the correct FSB clock frequency of the CPU as before, while the chipset is led to believe that a CPU with FSB 533 is involved.
This strategy is illustrated by the diagram above. Furthermore, it has to be confirmed that the memory clock works synchronously with the FSB clock (1:1 translation for the clock divider). In this case, the System Memory Frequency Select (SMFREQ) has to be adjusted accordingly. In addition, there are a few modifications in some BIOS registers that we won't get into at this point. The fact is that BIOS in the version 1007.001 already has modifications so that PAT is activated in any case. What's confusing is the older BIOS beta 1006.010, which only activates PAT with press samples. The version for end users can only profit from PAT starting with BIOS 1007, for which the software has been available since June 2, 2003.
