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Developments in system main memory (also known as RAM - random access memory) had been mostly linear until AMD and Intel introduced dual channel controllers in 2003. In the server space, you can also find Xeon platforms (Bensley or the latest Stoakley platform for 45 nm processors), which utilize a quad channel memory controller.
Memory modules, as opposed to installing individual memory chips, were introduced to facilitate memory deployment in the 1990s. The first Single Inline Memory Modules (SIMMs) had 30 pins and were eight bits wide, which meant that pairs had to be used for 286 and 386SX computers (16 bit machines), and four SIMMs were required for 386DX systems and up (32 bit architectures). 30-pin SIMM and SIPP modules were available at 256 kB to 4 MB each, and they were replaced by the 72-pin PS/2 SIMMs in the mid ’90s. The fact that at least two or four modules had to be used has nothing to do with parallelism; it is only because the system bus width had to be matched.
72-pin SIMMs were used for fast page mode DRAM (FPM), which was quickly replaced by Extended Data Out (EDO) memory in the late 1990s. Although 64 MB PS/2 SIMMs existed, they typically maxed out at 32 MB per module. EDO delivers better read performance when multiple data is read out of a page, where the row address doesn’t have to be changed. EDO reached a peak bandwidth of 266 MB/s.
EDO was replaced by synchronous DRAM (SDRAM) on 128-pin DIMMs (64-bit data bus at 3.3 V), where the clock is defined by the system bus or the memory controller. First generation PC66 memory was already twice as fast as EDO-DRAM, and following generations scaled nicely: PC100 and PC133 became popular. After that, double data rate (DDR) SDRAM was introduced, using 184-pin DDR-DIMMs. These reduced the voltage to 2.5 V and doubled performance by transferring data on the rising as well as falling edge of the clock signal, at up to 200 MHz base clock speeds (DDR400). DDR2 memory on 240-pin DIMMs as well as DDR3 is still based on this same technology, but offers a larger prefetch and much increased clock speeds of up to 400 MHz with DDR2 (DDR2-800) and projected 800 MHz for DDR3 (DDR3-1600).
All of these technologies worked on a single memory channel, which means they increased bandwidth over previous generations by widening the memory bus and by accelerating memory speed.