Page 1:Intel’s Ultramobile Future Arrives
Page 2:Little, Less, And Loving It
Page 3:Checking Checkboxes
Page 4:The Moorestown Breakdown
Page 5:Platform And Process
Page 6:Processor Power
Page 7:New Power States
Page 8:Graphics And Video
Page 9:Display And Memory
Page 10:Langwell Platform Controller Hub MP20
Page 11:Briertown Mixed Signal IC
Page 12:The Experience
Page 13:Why Moorestown Matters
New Power States
Another improvement over Silverthorne is Intel’s addition of “Enhanced Geyserville,” or Intel Enhanced SpeedStep Technology. This is part of how Lincroft chips are able to run at 200 MHz, while Silverthorne bottomed out at 600 MHz.
Just as importantly, Lincroft now uses power gating across 19 “islands” within the processing core. We’ve seen similar power gating employed in recent Core i-series designs, where current is cut to an entire block within the CPU in order to prevent the leakage that increasingly plagues circuits the smaller they get. This is a much more granular and effective approach than the older method of dropping power (and thus performance) en masse across the core, which still left leakage doors wide open. This was the model that Menlow used, wherein power was either in an on, off, or sleep state. There was nothing in between. With Moorestown, we can now control which islands are active or powered down.
The conventional CPU power states of C0 through C6 still carry forward into Lincroft and are now often collectively called S0. But one of the critical improvements in this generation is the addition of two new power states called S0i1 and S0i3.
S0i1 gets utilized during idle periods in which user is still classified as being interactive but may not be doing anything at just that moment, such as when looking at the home screen or reading a Web page. As you can see in the image above, the majority of islands in the CPU are powered off in S0i1. This delivers a 10% to 15% drop in power use while active. There’s about a 600 microsecond latency when entering the state and an exit target of 1.2 milliseconds.
S0i3 kicks in when the user isn’t actively using the device. Essentially, this is Lincroft’s standby mode, the state in which Intel estimates that a handheld or tablet will spend over 99% of its time over prolonged use. Only the SRAM, GPIO, and System Power Management islands receive any power. Entry latency is 450 microseconds while exit latency hits about 3.1 milliseconds. To get a sense of just how much power S0i1 cuts across the Linfield die, check out the the following image. Then imagine nothing but empty, unmarked blue save for two fields in the top-left corner. That's S0i3.
Intel draws the analogy of walking into a house at night. Under the old model, there was one light switch. You walked in the door, flicked the switch, and the whole house lit up, albeit with a rudimentary dimmer attached. Under Lincroft, you get to turn on lights only in the rooms you need as you walk into them. When you exit the room, out go that space’s lights automatically.
Taken all together, the power improvements in Moorestown yield a 2x to 3x reduction in active platform power compared to Menlow, and a 50x reduction in idle platform power. Without this, Intel couldn’t have met its battery life objectives and become a real contender in the ultramobile market.
- Intel’s Ultramobile Future Arrives
- Little, Less, And Loving It
- Checking Checkboxes
- The Moorestown Breakdown
- Platform And Process
- Processor Power
- New Power States
- Graphics And Video
- Display And Memory
- Langwell Platform Controller Hub MP20
- Briertown Mixed Signal IC
- The Experience
- Why Moorestown Matters