Called Hybrid Memory Cube (HMC), the technology represents a logic layer with a stack of memory chips that are vertically connected with through silicon vias (TSVs). According to Micron, the number of contacts as well as short distances enable dramatically higher data transfer rates than today's memory architecture. The prototype shown at Hot Chips was rated at 128 GBps.
In comparison, current DDR3-1600 devices deliver 12.8 GBps. Micron claims that a single HMC could deliver about 20 times the bandwidth of a DDR3 module, while it consumes substantially less energy - only 10 percent of the energy per bit that DDR3 uses. According to the manufacturer, the architecture also requires about 90 percent less space than current RDIMMs.
Micron does not provide any information when HMCs will be available for purchase, but it pitches the technology as a way to break through the "memory wall", which is a term that commonly refers to the relatively small gains in memory efficiency and performance gains. The memory is designed to be used either to be used in close proximity to the CPU in performance-based systems or as far memory in systems that are built for better power efficiency.
It'd be wise for chip-makers to look into developmental partnerships with Micron on this one. Getting this kind of tech integrated into CPUs and/or Northbridges, or even simpler SOC designs would be pretty huge.
I'd be surprised to see it on the market any time soon.