Chicago (IL) - Intel recently informed system that it will introduce a sequence numbering system for its server platforms covering Xeon and Itanium 2 processors, beginning with the arrival of next-generation dual-core products. Xeons will be integrated in the 5000 (DP) and 7000 (MP) series. The future "Montecito" chip will be marketed as Itanium2 9000 with up to 1.8 GHz clock speed and a power consumption as little as 62 watts.
With the sequence numbering system in its second year in the consumer segment, Intel feels confident enough to extend the strategy into corporate and enterprise markets. According to a briefing, the company gave to system builders both Xeon and Itanium2 models will get the new model numbers beginning with upcoming product generations.
Intel apparently will not change the current Itanium brand for its new dual-core Montecito processor. The 1.7-billion transistor processor, the most complex processor built to date, will continue to listen to the Itanium2 name. Consumers will be able to differentiate these chips from existing Itanium2 chips through its 9000-series model number.
The 90 nm Montecito will be launched in the first quarter of next year as 9010, 9020, 9030 and 9040 model, which will be clocked at 1.50, 1.60, 1.66 and 1.70 GHz and offer 400 and 533 MHz FSB versions. The FSB 667 versions 9011, 9021, 9031, and 9041 will follow in Q2. The flagship model of the Itanium2 family will be the 9041 (1.6 GHz, FSB 667) with 18 MByte L3 cache and the 9055 (1.80 GHz, FSB 400/533/667) with a whopping 24 MByte. With the arrival of a new power management technology that is codenamed "Foxton" and is most likely to debut with the Itanium2 "Montvale" in the second half of 2006, Intel will increase clock speeds up to 2 GHz.
There is also news for most other server platforms. The first dual-core Xeon MP, code-named "Paxville" will debut as versions 7020, 7030, 7040 and 7041, ranging in lock speeds from 2.67 to 2.8 GHz. The 90 nm processors will carry 2x1 MByte or 2x2 MByte of L2 cache and support FSB 667 (7020, 7040) and FSB 800 (7030, 7041). All Paxville chips will support demand based switching.
Volume server products, consisting of the current Xeon DP, will receive a 5000-series sequence number starting in Q1 of next year. This processor, code-named "Dempsey", will launch with clock speeds between 2.8 and 3.8 GHz and support FSB 667 and 1066. Dempsey is a 65 nm chip with a power consumption less than 105 watts and up to 4 MByte of L2 cache. A low power version of this chip code-named "Sossaman" will be designed for a power envelope of 31 watts and consume little more power than a Pentium M processor. Sossaman is likely to be based on a 2 GHz version of the mobile dual-core "Yonah" and therefore will not support 64-bit applications.