Unofficial information that Intel's upcoming codenamed Meteor Lake processor is set to feature L4 cache has been floating around for some time now. Now, a new Intel patent found by VideoCardz indicates that Intel has prepped a codenamed Adamantine L4 cache tile that it may use for some CPUs. This IC could compete against AMD's 3D V-Cache in certain applications, but the chiplet will not be used solely as a performance booster.
Typically, caches serve to increase the performance of the memory subsystem by rapidly providing compute cores with necessary data. But there are other use cases too, as large caches can store a lot of data. The patent suggests that Intel's Adamantine (or ADM) cache can improve communication not only between the CPU and memory but also between the CPU and security controller. For example, the L4 can be used to improve boot optimization and even preserve data from caches at reset to improve loading times.
Windows 10 and Windows 11 loading times are fairly quick on Intel's platforms even today. But Intel believes that with memory available at reset, faster and more efficient BIOS solutions can be developed for modern devices like car infotainment systems and household robots. Automotive and robotic designs closely link SoC security with firmware phases, ensuring platform security. Failing to follow recommendations stops the platform from booting to the OS, thus reducing attack risks and protecting confidential blocks, which is crucial for cars and robots.
While the patent itself does not mention Meteor Lake, images supplied with it clearly demonstrate a processor with two high-performance Redwood Cove and eight energy-efficient Crestmont cores on one tile produced on Intel 4 fabrication process, a graphics chiplet based on Intel's Gen 12.7 architecture (Xe-LPG), an SoC tile containing two more Crestmont cores, and an I/O chiplet interconnected using Intel's Foveros 3D technology. The description corresponds to that of Intel's Meteor Lake processor. Meanwhile, the Adamantine L4 cache can be used for a wide array of applications beyond Meteor Lake.
Here is Intel's description of Adamantine:
To be utilized by the Meteor Lake-M and Meteor Lake-P chips which target the mobility platform. Intel Arc Xe-LPG GPUs will be the main beneficiary of the Adamantine L4 cache IMO.
Actually in some of the recent patches, as discovered by Phoronix (can't find the proper link now), it was revealed that, unlike the previous designs, Intel Meteor Lake GPU cannot utilize the LLC on the chip which was previously shared by both the CPU and GPU.
As such, the Adamantine L4 cache will play a huge role to assist the performance of Meteor Lake chips in graphics workloads.
But of course, Adamantine L4 cache can also be used by the Compute Title (CPU Cores), which are made up of Redwood Cove (P-Core) & Crestmont (E-Core) hybrid configurations, leading to faster boot times and overall lower latencies compared to moving data to the primary DRAM.
As long as that is not all it helps then a L4 cache can be good
I never cared about my PC's boot time since I usually only reboot my PC once every 2-3 months.
With Intel bringing their implementation on the way, you can bet that AMD will have their implementation.
It's going to be a great day when everybody starts using L4$ SRAM to benefit their CPU's =D
On low power mobile the benefit the iGPU would get is just not worth all of this silicon. (for example Xe > Broadwell iGPU. DDR5 has enough bandwidth for mobile stuff, you can see that with AMD's bigger iGPUs) Also without a dGPU the extra cache doesn't help that much.
For a low powered mobile part the extra cache for extra performance in things the chip won't be doing doesn't make much sense. Power savings does.
Some Arrow Lake or Lunar Lake desktop chip with faster P-cores and a 256MB L4 does sound pretty appealing though and if they have it in MTL, even if it isn't used the way I want, the manufacturing experience from making and using it will help reach the goal of using a large L4 properly.
The SoC die has 2 additional Crestmont cores, even though it's meant to be made on a larger process node!
The L4 cache die is off to the side of the SOC die, not directly connected to either the CPU or GPU tiles. I wonder if they at least put the tag RAM in the SoC tile.
This sentence strikes me as very odd:
"Value is added for high end silicon with higher pre-initialized memory at reset, potentially leading to increased revenue."
Do they literally mean "revenue" in the sense of better sales? Um, how exactly does "higher pre-initialized memory at reset" translate into that, and what does it have to do with the L4 cache?
Is this something to do with the boot phase before the DRAM controller is initialized? So, they want to rely on the L4 cache tile to hold the entire pre-boot firmware image, and that lets the offer better hardware security?
I assume they're talking about the LLC of the CPU die.
I think there's a good chance that AMD will keep the GPU on its own Infinity Cache slice.
That's an interesting point - they could power down the CPU tile and just run the Crestmont cores on the SoC tile. Likewise, they could power down the L4 tile - I know some phone SoCs power down parts of their cache hierarchy to save energy.
Disagree. A big part of Apple's power savings has been through more aggressive use of cache. When the system is running under high load, it's much more efficient to go to cache than DRAM.
Also, I disagree on the bandwidth aspect, as iGPUs are famously bandwidth-limited. That's why AMD went from 11 CUs to 8, in more recent SoCs with Vega. If Intel is scaling up its iGPU past 96 EUs, then they'll need the additional bandwidth.