Rambus' HBM2E Memory Controller & PHY Offer Chipmakers Cost-Effective Designs

The latest generation of high-bandwidth memory, HBM2E, is around the corner. Now that Samsung has started mass production of its HBM2E memory stacks, Rambus has unveiled its controller and PHY (physical interface) designs.

Announced last week, Rambus' controller and PHY designs enable specifications that fall right in line with the JEDEC HBM2E standard. The controller supports up to 12-layers of 3D stacked DRAM memory. Each level of DRAM in HBM2E can fit up to 24Gb, which means individual HBM2E stacks will come in capacities of up to 36GB at full height.

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Similarly, the interface specs a 1,024-bit width, which paired with a 3.2 Gbps memory frequency translates to an aggregate memory bandwidth of 410 GBps.

Rambus' place in the market is that of an IP licensor. It doesn't physically build the controller or interfaces, but instead licenses its designs out to chipmakers who want to integrate HBM2E into their silicon. For smaller manufacturers, licensing HBM2E controller and interface designs is significantly more cost-effective than the R&D costs of creating their own designs. 

That being said, HBM2E will still be an expensive memory product. GDDR6, as found in most modern-day consumer-grade products, is much cheaper and will continue to dominate the market for a long time. 

HBM2E is expected to make its biggest impact in artificial intelligence and high-performance computing applications, where the extremely high memory bandwidth is a hard requirement and there's limited board space on GPUs.