Ryzen 4000 Detailed: Purported AMD Confidential Documents Outline Zen 3's Inner Workings

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A teaser before October 8.

AMD Ryzen 4000-Series Processor

AMD Ryzen 4000-Series Processor (Image credit: AMD)

While we wait for AMD's Zen 3 announcement on October 8, hardware leaker CyberPunkCat has just sent us a sneak preview of what's to come. AMD's processors already occupy five of the six positions in our Best Gaming CPUs list, and Zen 3 will likely solidify AMD's position even more.

The document, which dates back to June 10, appears to come from AMD's secret vault. While the information looks legit, we still recommend you approach it with a bit of caution. However, the info does align with what we already know about the Zen 3 microarchitecture for an accidentally-posted AMD presentation. 

With that in mind, the document is a Processor Programming Reference (PPR) guide for AMD's Family 19h Model 21h B0. As a refresher, Zen(+) and Zen 2 belong to Family 17h, so Family 19h should be for Zen 3.

Little surprise, Ryzen 4000-series (codename Vermeer) processors will retain the multi-chip module (MCM) design, otherwise known as a chiplet design. Zen 3 will package two core complex dies (CCDs) with a one I/O die (IOD) inside of a chip package. On the outside, the setup looks identical to Zen 2, but it's not. The devil is in the details.

On Zen 2, each CCD houses two core complexes (CCXs), whereby each complex is comprised of four cores that share 16MB of L3 cache. According to the AMD document, Zen 3's composition is completely different - there's only one CCX inside each CCD. The CCX possesses eight cores that can either run in single-thread (1T) or two-thread SMT (simultaneous multithreading) mode (2T), amounting up to 16 threads per complex. Since there's only one CCX now, all eight CPU cores can now directly access the 32MB of shared L3 cache.

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AMD Ryzen 4000
AMD Ryzen 4000(Image credit: CyberPunkCat)

Essentially, the amount of L3 cache remains the same at 32MB per CCD on Zen 3 as on Zen 2. On Zen 2, the four cores inside each CCX only have direct access to 16MB of L3 cache whereas on Zen 3, all eight cores within the CCX share the same 32MB of L3 cache. The revamped design should lower latency substantially and improve overall instruction per cycle (IPC) on Zen 3 parts.

In terms of core counts, Zen 3 seems to paint a similar picture as Zen 2. The flagship Ryzen 4000-series part, potentially the Ryzen 9 4950X , will likely max out at 16 cores and 32 threads, just like existing Ryzen 9 3950X. However, you can expect improved clock speeds on Zen 3 as early engineering samples of the Ryzen 9 4950X purportedly already boost up to 4.9 GHz when the previous Ryzen 9 3950X tops out at 4.7 GHz.

As per the information inside the document, Zen 3 features two unified memory controllers (UMC), one per channel. Each channel supports up to two DIMMs. There is also mention of the scalable data fabric with the capacity to handle up to 512GB for each DRAM channel. In regards to memory speeds, Zen 3 processors arrive with native support for DDR4-3200, in the same vein as Zen 2. 

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Zhiye Liu
Zhiye Liu
News Editor and Memory Reviewer

Zhiye Liu is a news editor and memory reviewer at Tom’s Hardware. Although he loves everything that’s hardware, he has a soft spot for CPUs, GPUs, and RAM.

10 Comments Comment from the forums
  • NightHawkRMX
    Hmm. Less latency coupled with more IPC will be very helpful to performance.
    If AMD can manage even more clock speed, that's a bonus.
    Reply
  • Gillerer
    Essentially, the amount of L3 cache remains the same at 32MB per CCD on Zen 3 as on Zen 2. On Zen 2, the four cores inside each CCX only have direct access to 16MB of L3 cache whereas on Zen 3, all eight cores within the CCX share the same 32MB of L3 cache. The revamped design should lower latency substantially and improve overall instruction per cycle (IPC) on Zen 3 parts.
    (emphasis mine)

    It's not just direct access; On Zen 2, the only L3 cache each core has access to is the 16MB residing in the same CCX.

    That means that the latency implications should be slightly less than presented in this article: Even now there is never cross-CCX cache access, so the improvement comes solely from more accessible L3 (less trips to RAM). On the other hand, larger cache typically results in increased access latency. We'll have to see how it goes here.
    Reply
  • tiggers97
    Anything new on the X670 chipset? It's been quite a few months now since anything has been mentioned.
    Reply
  • Brane212
    IOW, new details are that there are no new details.
    Reply
  • InvalidError
    NightHawkRMX said:
    Hmm. Less latency coupled with more IPC will be very helpful to performance.
    Well, when you do an IPC evaluation, the increased effective local cache size, reduced average latency and any other platform changes also get baked into the IPC figure - uncore improvements improve IPC by letting cores waste less time waiting for stuff.
    Reply
  • Flayed
    Hmm kind of tempting to raid the piggy bank for an 8 core Zen 3 when they show up
    Reply
  • Makaveli
    Flayed said:
    Hmm kind of tempting to raid the piggy bank for an 8 core Zen 3 when they show up

    I will be grabbing one to replace my 3800x :)
    Reply
  • cryoburner
    Brane212 said:
    IOW, new details are that there are no new details.
    Yeah, this confidential document leak seems pretty boring as far as confidential document leaks go. I didn't see anything that wasn't already known, or at least rumored months ago. The only thing it really seems to verify is that they are moving to a single 8-core CCX per chiplet, but that was already expected for quite some time.
    Reply
  • Olle P
    Gillerer said:
    It's not just direct access; On Zen 2, the only L3 cache each core has access to is the 16MB residing in the same CCX.
    That means that the latency implications should be slightly less than presented in this article: Even now there is never cross-CCX cache access, so the improvement comes solely from more accessible L3 ...
    Consider that most of the CPUs sold are Ryzen 3, 5 or 7.
    With Zen 2 these have the L3 cache divided between two CCX s and with Zen 3 all cores have direct access to all L3. Any cross-CCX latency will only affect the few Ryzen 9 sold.
    Reply
  • Gillerer
    Olle P said:
    Consider that most of the CPUs sold are Ryzen 3, 5 or 7.
    With Zen 2 these have the L3 cache divided between two CCX s and with Zen 3 all cores have direct access to all L3. Any cross-CCX latency will only affect the few Ryzen 9 sold.

    I see your point. I guess I got hung up on the latency improvements presented right after L3 cache change, which gave the impression that that was the main reason for improvements.
    Reply