A report citing semiconductor industry sources indicates that TSMC reportedly has difficulty with its 3nm process yields. Taiwan's DigiTimes says that if the 3nm yield problem continues, many customers might extend their use of the 5nm process node. In addition, TSMC's struggles could impact the product roadmaps of the PC world's favorite names like AMD and Nvidia.
It's essential to take the report with a pinch of salt. The people in the know might be correct, but TSMC hasn't publicly admitted any N3 delays so far. On the contrary, it has asserted that it is "on track with good progress."
The source report's critical rumor is pinned upon TSMC, finding it very difficult to achieve satisfactory yields with its 3nm FinFET processes. It explains that TSMC has "continuously revised" its 3nm offerings, and the foundry is seemingly doing this to find a sweet spot for yields (the percentage of chips that are not faulty). The latest TSMC introduction is N3E, a lower-cost version of TSMC's 3nm manufacturing process, which surprised industry watchers by arriving a year after N3. TSMC also makes N3B processors for some customers, depending upon design and cost constraints. Despite TSMC's process wrangling, outlined above, and "constant revision," the insiders say yields continue to remain lower than expected.
Due to the 3nm family issues, some TSMC's customers are looking at rejigging plans, which means changing their roadmaps. In addition, customers like Apple and Intel have paid a lot to secure N3 process chips in the coming months. Other partners like AMD must not have felt the urgency or need for such lavish pre-payments so that they will feel the most substantial effect of TSMC's yield issues.
AMD's Roadmap Roadblock
The DigiTimes report says that AMD is one of the biggest customers of the TSMC 7nm family, which offers N7 and N6 process fabrication. AMD has just started to move parts to N6, such as the Ryzen 6000 series of processors for laptops. Newer GPUs will be coming out based on N6 output too.
AMD's subsequent big releases, such as the Ryzen 7000 series desktop processors and Genoa and Bergamo server processors, will all be based on the Zen 4 architecture and be fabricated at 5nm by TSMC. As a reminder, the TSMC 5nm process family will be referred to as N5 and N4 processes by TSMC. AMD had planned to go on to TSMC 3nm for Zen 5 and RDNA 4.
The report also mentioned Nvidia, saying that the green team was set to return to TSMC later this year and will use one of TSMC's 5nm processes for the RTX 40-series GPUs, having paid "billions of dollars" to secure this production allocation.
TSMC vs Samsung
The news outlet threw some interesting Samsung semiconductor business morsels into the article. While TSMC has various 3nm wrinkles to try and iron out, Samsung's progress is also rough, it asserts. Moreover, it comments that Samsung's recent 4nm Exynos 2200 debut wasn't the barnstormer it had teased.
Samsung has a significant hurdle to leap over with its upcoming 3nm process, too. The South Korean tech giant moves to the Gate-All-Around FET (GAA) transistor architecture. It's quite a change to make, but it should make advances later down the pipeline easier. However, its transition to 3nm will be all the more tricky before it can reap the rewards.
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Which isn't necessarily a bad thing if there's process refinements on the current node and better designs to maximize the use of said process node.Reply
We are approaching a hard limit, as transistor features will never be smaller than 0 nm. Everyone will run into process issues at some point.Reply
Doesnt this first affect apple? They use the newest process first. Like why is AMD first to be mentioned, click bait? Once apple is done with 3nm it should be perfect for amd.Reply
Samsung's recent 4nm Exynos 2200 debut wasn't the barnstormer it had teased.
That's an understatement, it's slower than the 2019 iPhone 11...which also whips my Galaxy S10+...
Slow news day? Not loving the boy who cried wolf aspect of this story but it seems to be the norm lately.Reply
The OP is super vague with no clarifying details on shipped units, process types, etc.
The newest TSMC N3 node advancement is EUV (ultraviolet). Announced end of Q3/21. Growing pains w a new node design aren't exactly uncommon. OP doesn't reference EUV in an article dated today. Apple and Intel are buying 3nm parts today.
So.. AMD and Nvidia still have options, imo.
It may affect AMD's roadmap, but I agree this is going to hit Apple and likely Intel hardest since they appear to be the biggest buyer of N3 at this point in time. Only companies will very deep pockets will meddle with cutting edge node. AMD most likely will stick with their next best advance node strategy.GoldenBullet said:Doesnt this first affect apple? They use the newest process first. Like why is AMD first to be mentioned, click bait? Once apple is done with 3nm it should be perfect for amd.
I can distinctly remember people saying the same thing about sub-130nm lithography. "It's as small as light gets! It's a hard limit!"TEAMSWITCHER said:We are approaching a hard limit, as transistor features will never be smaller than 0 nm. Everyone will run into process issues at some point.
GoldenBullet said:Doesnt this first affect apple? They use the newest process first. Like why is AMD first to be mentioned, click bait? Once apple is done with 3nm it should be perfect for amd.
That's mean AMD and nvidia will be thrown under the bus by TSMC once again like what happen with 20nm. With 20nm TSMC end up giving 100% towards apple once it is hard for them for make 20nmHP process that needed by AMD and nvidia for their high end stuff. This end up forcing both AMD and nvidia sticking with 28nm. So we probably not going to reach a point where "things are iron out after apple use 3nm which allow AMD or nvidia to use the node for their product". Remember apple are not making 500mm2 (or bigger) type of chip that consume 300w or more.
As for the supposed "3nm yield issues" rumored about by some anonymous sources in the article, there could potentially be some truth to them, but even if so, the suggestion that they "May Derail AMD's CPU Plans" is little more than baseless speculation, and is probably inaccurate. Keep in mind, AMD's current chiplet design is based entirely around making the best of low yields. It allows them to use a single compact chiplet across everything from entry-level CPUs to massive server processors. Is half of an 8-core chiplet defective? No problem, disable those cores and put it in a part utilizing four of them. The non-core portions of the processors are built on larger, established process nodes, and not as subject to yield issues. Needing to disable a portion of a large number of chiplets could potentially impact profits to some extent, but the markup they put on their current processors is quite large, giving them a lot of room to adjust for that while still being profitable. And from the sound of it, their upcoming GPU designs will also be moving to a similar multi-chip approach.Reply
That's like stating that a microscope will never show features "smaller than 0 meters". You are effectively saying that things can't be smaller than an infinitely small size. : PTEAMSWITCHER said:We are approaching a hard limit, as transistor features will never be smaller than 0 nm. Everyone will run into process issues at some point.
Of course things will continue to get harder to shrink the closer you get to the molecular limits of the materials, but it's probably also worth noting that the current "nm" ratings that are thrown around are more marketing numbers than anything, and the actual smallest features in a "3nm" chip will still be quite a bit larger than 3nm. I think it's been a couple decades since the process node names were an accurate measure of transistor gate sizes, and the actual transistor gate pitch for TSMC's current "5nm node" is somewhere around 48nm. So, it's likely they'll continue releasing marketing names for their nodes that imply feature sizes below 1nm within the next decade or so, even if that's not actually based on any real-world measurement. Of course, there is also likely still a lot of room for things like 3D chip design processes to improve efficiency and performance further even if the actual size of transistors isn't changing much. Along with improvements to the manufacturing process that could potentially reduce the cost per transistor without necessarily making them smaller.
130nm is only the limit for simple UV lithography.jkflipflop98 said:I can distinctly remember people saying the same thing about sub-130nm lithography. "It's as small as light gets! It's a hard limit!"
The problem with 3nm is you cannot afford many out-of-place atoms when traces and other features are under 10 atoms wide. This is a hard physical limit, the practical minimum number of atoms necessary to make stuff work. At this point, chips failing due to atomic decay become a real concern.