What Took So Long?
Power users have been maximizing memory almost since the beginning of personal computing, often attempting to make workstation-class programs run as well on home computers as they do on lab machines. Memory manufacturers gladly filled demand by producing non-ECC memory at server-sized capacities, easily reaching the 1GB per module capacity limit of DDR1 many years ago. That 1GB limit became the baseline for high-capacity DDR2 modules almost immediately after compatible platforms launched, and that technology’s 4GB per module limit was reached within a few years. With the trend set, many of us expected 4GB DDR3 performance modules to hit the market way back in 2007 and the maximum 16GB capacity to be reached soon. However, DDR3 capacities didn’t follow former trends.
We could speculate about how demand for increased capacities might have dropped off as user expectations reached a plateau with 1080p animations or 12 megapixel images, but that still doesn’t explain why, for nearly two years, DDR2 was the only option for most users who wanted really high memory capacities in their PCs. DDR3 users were forced to use four modules (dual-channel) or six modules (triple channel) to reach 8GB and 12GB capacities, and anyone who wanted 16GB or more had to wait over a year for the release of super-expensive 4GB DIMMs. Even as 4GB DDR3 modules for notebooks became common, desktop DDR3 users faced the fear of paying eight times as much to double their memory capacity.
The breakthrough came late last fall, when G.Skill introduced several high-density kits priced “only” four times as high as similar parts half the size. Other manufacturers gradually followed, and today we finally have several 8GB two-module kits that most high-end builders can afford.
Rated at CAS 9 and priced between $400 and $500, manufacturer-approved data rates of 1,333 and 1,600 MHz appear to be the only noticeable difference between these modules. Curious to find the highest-performance parts within this budget range, we tested each set to find out the true limits of its stability, both at lower-latency and higher-frequency settings.
