Dynamic Power Coordination
As in the predecessor Banias and Dothan CPUs, these new processors can adjust core voltages and clock frequencies to meet changing application performance demand. Previously, this energy saving mechanism had been called Enhanced SpeedStep, but it had to be reworked and improved for the new dual core architecture. Intel describes this enhanced implementation with the catchphrase "Dynamic Power Coordination".
In this technique, the clock rate and core voltage applied to both cores is determined by the core that currently services the heaviest demand. If core 1 runs at 2 GHz, the other core runs at the same speed and voltage level, regardless of whether that core is executing some task or is idle. Only when core 1 reduces its clock rate can core 2 switch down to the same SpeedStep performance mode, assuming of course, that core 2 has no more to do than core 1 at that particular instant.
Dynamic Power Coordination
As just described, transitions from one SpeedStep performance mode to another are coordinated between the cores. This situation changes when both CPU cores are only minimally loaded and running at the minimal core clock rate. Intel designates this situation as "Lowest Frequency Mode", or "LFM".
The technical literature for the processor assigns these various performance and energy consumption levels using alphanumeric codes that run from C0 to C4. When the situation that produces LFM occurs, the general power management algorithm keeps core 1 active at the C0 level, but turns off the clock in core 2. This puts core 2 into the power-saving C2 level. If both cores are in Deep Sleep Mode (C3), the CPU (both cores) can be turned down further into DeeperSleep (C4) or even into Enhanced Deeper Sleep (DC4) modes.
It's not possible, however, for core 1 to be set to DC4, or perhaps C1, C2, or C3, and for core 2 to operate at maximum frequency at the same time. The overall voltage regulator simply won't permit this to occur. In so-called Enhanced Deeper Sleep mode, Yonah actually won't copy unused cache lanes back to system memory; it turns the L2 cache off entirely and lowers core voltage still further from levels set for Deeper Sleep Mode. This definitely helps conserve power.
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