It goes without saying that a 12-core CPU isn’t necessary for gaming. Indeed, when it comes to 3DMark’s Graphics component, the quad-core Sandy Bridge, Ivy Bridge, and Haswell processors are all faster than Intel’s upcoming Xeon E5.
However, the physics test spawns threads for physical and logical cores. Despite its lower clock rate and thermal ceiling, the Xeon E5-2697 V2 pulls down the highest Physics score.
The Core i7-4960X sports the same core configuration as its predecessor. Moreover, the Ivy Bridge architecture didn’t incorporate any instruction set extensions beyond Sandy Bridge’s design. Consequently, the -4960X doesn’t demonstrate any more alacrity in Sandra’s Arithmetic module. The eight-core Sandy Bridge-EP and 12-core Ivy Bridge-EP processors, on the other hand, are quite a bit faster in this synthetic metric.
The same applies to Sandra’s Multimedia test. Intel’s Haswell architecture fares well in the integer component thanks to its AVX2 support, even outperforming Core i7-4960X. However, more on-die resources give Intel’s eight- and 12-core CPUs an advantage. The floating-point tests are outright rocked by both of the Xeon processors.
As with Ivy Bridge-E, Ivy Bridge-EP supports four channels of DDR3-1866 memory. There’s a bit of difference between the quad-channel configurations. But, in essence, you’re seeing the high-end platforms doubling the dual-channel mainstream systems.
Intel’s Core i7-4770K came close, but we now have our first L1 data cache bandwidth result in excess of 1 TB/s. Of course, the Haswell architecture achieves its result through a doubling of L1 throughput compared to Ivy Bridge (this checks out; compare the Core i7-3770K).
The eight-core Sandy Bridge-EP-based Xeon E5-2687W comes close to matching Core i7-4770K by leveraging twice as many cores in this aggregate metric. Ivy Bridge-EP surpasses it with another four cores. Just imagine what a Haswell-based implementation could do!
L2 cache bandwidth aggregates as well, which is why Sandra measures almost 800 GB/s across all 12 cores. L3 is of course shared between the cores, though additional stops on the ring bus contribute to greater throughput in this case, too.