GDDR5 uses an 8-bit prefetch, like GDDR4, but ushers in more innovations. First of all, GDDR5 uses two clock frequencies, CK and WCK, the latter being twice as fast as the former. Commands are transferred in SDR at frequency CK; addresses are transferred in DDR at frequency CK; and finally, data are transferred in DDR and at frequency WCK. In the case of the Radeon HD 4870, which uses GDDR5 at 900MHz, commands are transferred at 900MHz SDR, addresses at 900MHz DDR and data at 1800MHz DDR.
This approach reduces problems related to signal quality during transmission of commands and addresses while enabling very high frequencies for data transmission. Unfortunately, the higher frequencies also mean higher error probability. So to ensure the validity of the data transmitted, GDDR5 implements an error detection mechanism based on the one used by networks. If an error is detected by the memory controller, the command that caused it can be re-executed.
So, AMD and Nvidia have made very different choices in order to meet the bandwidth needs of their GPUs, and those choices are related to their divergent visions of graphics processors. Nvidia, faithful to its concept of enormous monolithic GPUs, could afford to use a 512-bit bus, thus avoiding the supply problems that generally accompany the use of a leading-edge memory technology. Conversely, from the inception of the RV770, AMD has concentrated its efforts on a GPU with a reduced die size for high-end cards. As the AMD engineers told us, the first version of the RV770 was supposed to have no more than 480 ALUs, but the GPU proved to be "pad limited" in that configuration.
Consequently, AMD was able to offer the GPU it just released, with 800 ALUs that are almost “free” in terms of die surface area. It’s a problem Nvidia will face in developing its GT200b using a finer process: how to keep a 512-bit bus on a smaller die without being pad limited. With the preceding generation, Nvidia was forced to abandon the 384-bit bus when it moved from the G80 (0.08µ) to the G92 (0.065µ). So there’s a good chance that will also happen with the 512-bit bus. But this time, Nvidia may rely on GDDR5 to compensate for the loss of bandwidth.