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Future Promise for Graphics: PCI Express

Bridge It - NVIDIA's HSI Bridge, Continued

Which brings us to the final argument against a PCI Express -> AGP bridge, namely upstream performance (say it with me - real-time HTDV video editing). Here, the AGP bus can only offer a memory bandwidth of 266 MB/s, at least when using PCI Writes. However, when AGP Writes are used, the bus has the full memory bandwidth at its disposal, meaning 2.1 GB/s at AGP 8x and a full 4.2 GB/s in the case of NVIDIA's internal 16x AGP link. This changes nothing about the major disadvantage compared to PCI Express, namely that an upstream eats into the memory bandwidth available to the downstream. Additionally, there is no such thing as guaranteed bandwidth on the AGP bus, which can become a problem when using data streams such as video data (ta-dah!). For cases like this, the AGP 3.0 specification offers what's called the isochronous operation mode.

The question remains as to how well AGP writes function in practice - think compatibility here. Not all chipsets available in the market today support AGP writes. In that case, NVIDIA's HSI bridge would switch down to the slow PCI writes.

The long and short of it is that using an AGP graphics chip with an HSI bridge should have no negative impact on 3D games. Upstreams from the card to the system memory can also utilize the full bandwidth, thanks to AGP writes. Even if PCI writes are used for compatibility reasons, the system could still transfer an uncompressed HDTV stream in 1080i (240 MB/s) over such a solution. The HSI bridge would only run into trouble if there were simultaneous upstreams and downstreams competing for memory bandwidth. Seen from a realistic perspective, applications that would require such a scenario are exceedingly rare. With the exception of the real-time HDTV editing mentioned above, nothing really comes to mind.

Does that make "real" PCI Express devices unnecessary? Not really, since software will begin to take advantage of the higher memory bandwidth offered by the new system bus in the long run. It's a case of "If you build it, they will come!" For example, engineers are already working on a way to harness the concentrated floating-point power of modern graphics chips for other applications, effectively using the graphics chip as a co-processor. In such a scenario, the ability to read and write over the bus simultaneously would be of paramount importance to prevent delays.