Intel Discloses New Itanium Poulson Features

Tukwila, the current 65nm Itanium 9300 series, is overdue for a replacement in big iron computer systems. We already know that Poulson is still scheduled for a 2012 launch, and that it will be built in 32nm, integrate 3.1 billion transistors, a 12-wide issue architecture, up to 54 MB on-die memory as well as eight CPU cores with support for eight more virtual cores via Hyper Threading.

Adding to the information disclosed early this year at the ISSCC 2011, Intel revealed at the Hot Chips conference that the processor will ship with Instruction Replay Technology (IRT) as an enhancement for RAS - and become Intel's first processor that supports Instruction Replay RAS. The technology uses a new pipeline infrastructure to detect "transient errors in execution." IRT enables Poulson to re-execute instruction and recover or avoid instruction errors.

Poulson also adds dual-domain multi-threading that finds its way into the CPU's Hyper Threading. According to Intel, the new feature will enable independent front and backend pipeline execution, improve the efficiency of multi-threading and squeeze more performance out of the chip. Additionally, Itanium is getting new instructions to enhance integer operations, as well as higher parallelism and multi-threading capabilities with expanded data access hints, expanded software prefetch and thread control.

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