The world’s first RISC-V laptop gets a big upgrade — DeepComputing doubled the core count, increased clocks to 2 GHz, and added AI capabilities

DC-ROMA RISC-V Laptop II
(Image credit: DC-ROMA)

DeepComputing, the maker of the DC-ROMA RISC-V Laptop, just released an upgrade of its groundbreaking RISC-V-based computer. Dubbed the DC-ROMA RISC-V Laptop II, this revamped PC gets a SpacemiT SoC K1, which features 8 cores that run up to 2.0 GHz. This is a massive improvement over the previous version of the laptop, which only had a quad-core CPU limited to 1.5 GHz. The DC-ROMA RISC-V Laptop II also benefits from an AI Fusion Computing Engine and can be specced out to have 16GB of RAM.

The SpacemiT K1 chip is the same one found in the MuseBook, which the company launched recently and is focused on developers and engineers. While the MuseBook is a budget computer priced at just $300, the DC-ROMA RISC-V Laptop has a regular price of HK$7,820 or approximately $1,000, although it’s currently on sale at HK$5,865 or around $750.

Another big development with the Laptop II is its use of Canonical Ubuntu as its operating system. The previous version only supported openKylin and Debian, meaning you had to install an OS after purchase. On the other hand, the new laptop comes with Ubuntu right out of the box, making it easier for users to get up and running with the device.

RISC-V is an open-standard instruction set architecture developed at the University of California, Berkley, and uses the same reduced instruction set computer (RISC) architecture that Arm bases its designs on. The latter went on to dominate the consumer market, with most smartphones using Arm-based chips. Even Microsoft’s new Copilot+ PCs, which are powered by Qualcomm’s Snapdragon X SoCs, use Arm designs.

But even though RISC-V did not gain mass adoption in the consumer space, it still has a solid presence in data servers, high-performance computing, AI and machine learning, and even automotive systems. RISC-V is actually forecasted to grow quickly until 2030, especially as the demand for AI is growing exponentially.

RISC-V is an open-source architecture, so it’s much cheaper for companies to use their designs instead of licensing one from Arm, for example. Google is even reportedly set to use RISC-V as the base of its new custom AI silicon for its AI servers. Demand for this architecture is also driven by China, especially as it’s grappling with bans and sanctions from the US.

These sanctions have forced Chinese tech companies to look elsewhere for technologies, and RISC-V’s open-source nature is crucial for some of their plans. U.S.-imposed limitations have allowed the East Asian country to build innovative solutions based on this architecture. SiFive, the American semiconductor company behind the general-purpose cores of Google’s TPUs, even chose the faster Chinese Eswin SoC instead of an Intel processor for its HiFive Premier P550 development board.

Some of the news behind RISC-V’s advancement has put it in the spotlight of American lawmakers. The U.S. Department of Commerce then started to investigate China’s access to the open-source standard, and the risks that it poses to American technological supremacy. However, Calista Redmond, the CEO of Swiss-based RISC-V International, is adamant that RISC-V remain open. She said, “RISC-V is an open standard and has incorporated meaningful contributions from all over the world. As a global standard, RISC-V is not controlled by any single company or country.”

As long as RISC-V remains open to the world, many companies, both from the East and the West, will likely want to take advantage of its open-source nature. This will bring competition to Arm, Intel, and AMD, forcing these companies to innovate, not just in technological advancements, but in price efficiency, too.

Jowi Morales
Contributing Writer

Jowi Morales is a tech enthusiast with years of experience working in the industry. He’s been writing with several tech publications since 2021, where he’s been interested in tech hardware and consumer electronics.

  • bit_user
    The article said:
    RISC-V is an open-source architecture
    The article gets a lot right, but this one point we keep coming back to... it's an open and royalty-free standard. You can't have an open source standard, only open-source implementations. RISC-V doesn't require that implementations be open source, though there are a few.

    The article said:
    Calista Redmond, the CEO of Swiss-based RISC-V International, is adamant that RISC-V remain open. She said, “RISC-V is an open standard ...
    Yes! She obviously knows what she's talking about! Why don't you pay attention to how she said it??

    Tagging @PaulAlcorn
    Reply
  • Findecanor
    The SpacemiT X60 cores are in-order dual-issue.
    This is one of the first cores to support the RVA22 profile, plus it has a 256-bit vector unit. This means that its ISA support is pretty much feature-comparable to ARMv8.
    I have yet to see benchmarks actually compiled to that profile though. The single-core benchmarks I've seen have been compiled to RV64GC and been a little lower than the ARM Cortex A53 (also in-order dual-issue), but not by much.

    There are ARM A53 in the Raspberry PI 3, but half as many and clocked lower than in this laptop.
    Reply
  • DougMcC
    "and uses the same reduced instruction set computer (RISC) architecture that Arm bases its designs on"
    This is very poorly worded. Yes, they are both RISC architectures. No, they are not the SAME RISC architecture. The way it is currently worded would (IMO) suggest to most readers that you could run an arm binary on riscv.
    Edit: my suggestion "RISCV, like Arm, is a reduced instruction set computer (RISC) architecture,"
    Reply
  • bit_user
    DougMcC said:
    "and uses the same reduced instruction set computer (RISC) architecture that Arm bases its designs on"
    This is very poorly worded.
    You're right, but I didn't feel like nitpicking that particular aspect. If you know enough to parse it that closely, then you don't need to be told. If you don't know the subject so well, then you're probably not paying enough attention to that specific wording for the details to matter all that much.

    It probably would've been better for the article to just say they're both based on the RISC school of thought and put a link to the Wikipedia page on it. Saying any more gets down quite a rathole. For one thing, I've seen people debate whether AArch64 adheres to RISC orthodoxy well enough even to deserve being called RISC.
    Reply
  • abufrejoval
    I wonder if at these clocks binary translation on a x86 or ARM base wouldn't still be quite a bit faster.

    Sure you've got to admire that they are making the effort, but at A53 speeds you'd have to be a masochist to actually use that as a laptop.

    Having a Raspberry type test machine around for validations makes a lot of sense to me. If you could run that on an hardware enclave inside a normal laptop, that would be ok, too, especially when you travel.

    But dedicating a full shiny costly laptop to such a dog? I can't see them selling a lot of those and I can't see me swapping the compute module during different parts of the work day, either.

    And where are all the high-performance cores that so many startups seem to have had in the works? From EPI to the various Chinese hyperscalers?
    Reply
  • bit_user
    abufrejoval said:
    I wonder if at these clocks binary translation on a x86 or ARM base wouldn't still be quite a bit faster.
    It's hard for me to argue against this statement, but I can see a possible edge case. I think the "emulator" approach, if I may use that term loosely, might not match the timing behavior of real hardware. For people looking to do testing, tuning, and debugging on RISC-V, the gold standard is probably to do it on real hardware.
    Reply
  • abufrejoval
    bit_user said:
    It's hard for me to argue against this statement, but I can see a possible edge case. I think the "emulator" approach, if I may use that term loosely, might not match the timing behavior of real hardware. For people looking to do testing, tuning, and debugging on RISC-V, the gold standard is probably to do it on real hardware.
    In the olden days we used to have quite a few systems with expansion cards that allowed running an alternate CPU in your PC, but reusing most of the parts like RAM, disks, graphics cards, peripherals etc. , because at the time they were so very expensive. With those you booted your PC into an alternate personality, when requried.

    You had lots of microcomputer competitors e.g. Motorolas 68x00 on PCs, but IBM even sold tiny mainframes to go into your PC, long before Hercules (or Gene Amdahl) stared emulation or binary translation.

    Some others basically ran another pysical system inside and in parallel to your PC, much like a single VM with an alternate ISA, heck even my Apple ]



    Reply
  • steven_edwards
    bit_user said:
    The article gets a lot right, but this one point we keep coming back to... it's an open and royalty-free standard. You can't have an open source standard, only open-source implementations. RISC-V doesn't require that implementations be open source, though there are a few.


    Yes! She obviously knows what she's talking about! Why don't you pay attention to how she said it??
    Being pedantic about when it comes to open standards vs open source implementations aside, I am not sure I understand the second sentence or how it really relates or your choice of emphasis in your question.

    Can you clarify what you mean?

    How she said it seems pretty implied, that the open nature of Risc-V is a statement of fact and they are not ceding ground on control to any individual corporate/nation/state interest.

    Paying attention to how you are saying this just makes it more confusing. I don't understand why she was emphasized as it was in this context. There was really no need for it and if you had not emphasized it, then it would have been pretty straightforward as a good suggestion for journalism, to pay closer attention to tone and nuance and whatnot.
    Reply
  • bit_user
    steven_edwards said:
    Being pedantic about when it comes to open standards vs open source implementations aside,
    Nope - push that aside and there's nothing left. That was the entire point of my message. The authors on this site have an abhorrent track record of calling RISC-V "open source" or "an open source ISA". I simply don't understand why it's so difficult to grasp.
    Reply