DDR5 Specifications Land: Up To 8400 MHz, Catering To Systems With Lots of Cores

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It doesn't take a genius to figure out that DDR5 is nearing launch, but details have been surprisingly scarce. JEDEC, the organization behind memory standards, still hasn't finalized the DDR5 specification, but that's not to say that the memory makers don't know what they're doing, either. SK Hynix was kind enough to share some very juicy details in its newsroom yesterday, finally giving us some concrete information to share.

DDR4's memory bandwidth has become a major bottleneck as core counts on CPUs increased dramatically over the last few years -- and that's no surprise with that many cores battling over memory access. To address that need, DDR5 is built to offer significantly higher bandwidth that spans up to a whopping 8400 MHz.

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Niels Broekhuijsen
Contributing Writer

Niels Broekhuijsen is a Contributing Writer for Tom's Hardware US. He reviews cases, water cooling and pc builds.

  • coolitic
    "Samsung started mass production of its EUV DDR5 memory in 2021 "

    Uhhh, hello?
    Reply
  • N.Broekhuijsen
    coolitic said:
    "Samsung started mass production of its EUV DDR5 memory in 2021 "

    Uhhh, hello?
    Well spotted, thanks! All fixed.
    Reply
  • King_V
    coolitic said:
    "Samsung started mass production of its EUV DDR5 memory in 2021 "

    Uhhh, hello?

    What are you complaining about??! I mean, jeez, it's like you've never even heard of the Flux Capacitor option in cars! Don't judge, maybe Niels just happens to have one! :LOL:
    Reply
  • bit_user
    Presumably, on-die ECC is optional? Is there also any form of parity on the data/address bus?

    I also wonder how DDR5 latencies will compare with earlier memory generations (i.e. in terms of ns).
    Reply
  • jimmysmitty
    bit_user said:
    Presumably, on-die ECC is optional? Is there also any form of parity on the data/address bus?

    I also wonder how DDR5 latencies will compare with earlier memory generations (i.e. in terms of ns).

    I would assume that like most it will go up and will be the trade off for the higher speeds. But with time we will also see higher speeds and latency to go down from original highs.
    Reply
  • bit_user
    jimmysmitty said:
    I would assume that like most it will go up and will be the trade off for the higher speeds. But with time we will also see higher speeds and latency to go down from original highs.
    Here's an interesting comparison of DDR3 vs. DDR4. In their tests, the best DDR4 latencies never quite equaled the best DDR3, which is roughly as I expected.

    https://www.techspot.com/news/62129-ddr3-vs-ddr4-raw-bandwidth-numbers.html
    Note that two of their test systems are dual-channel, while the other two are quad-channel. Presumably, that explains the differences within the same memory speed grade. It's also interesting to see how much channel-doubling can compensate for lower memory speeds (note: 2x the channels isn't simply 2x as fast).
    Reply
  • spongiemaster
    Does this even matter besides in enterprise level applications? Especially on the Intel side, you're well into the who cares range of performance increases by the time you're in the mid 3000's. Moving from dual channel to quad channel also rarely results in any tangible improvements. Is there going to be a significant drop in latency?
    Reply
  • Chung Leong
    bit_user said:
    Presumably, on-die ECC is optional? Is there also any form of parity on the data/address bus?

    Sounds like it's not. They mentioned how ECC is going to improve node scaling by correcting single-bit errors. Presumably too many chips would not work reliably without it.
    Reply
  • bit_user
    spongiemaster said:
    Moving from dual channel to quad channel also rarely results in any tangible improvements.
    Is that still true for 8+ cores?

    I feel like Intel knew what they were doing, when they outfitted their server and workstation platforms with > 2 channels.

    spongiemaster said:
    Is there going to be a significant drop in latency?
    If you check the techspot link, the quad-channel setups have higher latency. Of course, they're also both 1 generation older than the 2-channel CPUs.
    Reply
  • JamesSneed
    To those saying faster memory isn't needed or more channels aren't needed, they surely are especially in the enterprise. You can't keep a 64 core CPU properly fed with dual channel 3200Mghz memory ie huge performance killing memory bottleneck. This is also why you don't see SMT4 because until memory bandwidth increases SMT4 is pretty pointless for many workloads as you would never keep the CPU fed unless you build in a ton of level 4 cache like the IBM power 9 chips did with 128 MiB of level 4 cache.
    Reply