A new leak by VideoCardz on Sunday suggests that Rocket Lake-S will be a major upgrade from any of Intel’s prior 14nm desktop silicon. Purportedly coming late this year on the 500-series platform, a leaked block diagram says the chips will bring a new core architecture, Xe graphics, 12-bit AV1, PCIe 4.0, twice the DMI 3.0 lanes and Thunderbolt 4. Notably, Intel's Software Guard Extensions (SGX) security instructions have been removed.
Rocket Lake-S (RKL-S) is set to succeed this spring's Comet Lake-S. In turn, it is expected to be succeeded by 10nm++ Alder Lake-S, which may feature Intel's big.Little hybrid architecture. This means that Rocket Lake-S will be Intel's last 14nm platform for the consumer market. For servers, Intel has planned Cooper Lake on 14nm++ this year.
New CPU Architecture, Retiring Grandpa Skylake
Before diving further, it is worth giving a small refresher about Rocket Lake. The codename first surfaced a year ago in two roadmap slides via Tweakers. The sides suggested that Rocket Lake would be manufactured on 14nm and come with both 14nm and 10nm graphics and up to 10 cores (more recent rumors have reduced this to eight cores).
This hinted at Rocket Lake using Intel’s long-announced mix-and-match chiplet strategy to mix a 14nm CPU with a 10nm graphics chip. Given the development work that this must have required and earlier comments at its 2018 Architecture Day about making its IP more flexible in terms of which process technology it is manufactured on, it has been speculated (first by Tom’s Hardware), that Intel might have backported one of its 10nm architectures to 14nm; possibly this year’s Willow Cove from Tiger Lake. This would bring architecture parity to the desktop, which is still based on Skylake through Comet Lake-S, while Intel works on its process technology.
This, indeed, seems to be the case, and would immediately be the highlight feature of Rocket Lake. The slide says it has “increased performance with new processor core architecture.”
Leaks had previously already come out suggesting that Rocket Lake would feature AVX-512 support. While this could have meant that Intel brought its server Skylake silicon to the desktop, Intel’s wording seems pretty unambiguous that it is not a Skylake derivative. Given the timing of Rocket Lake, our best bet would be that it comes with a backported version of Tiger Lake’s Willow Cove.
Intel claimed that Ice Lake’s Sunny Cove delivers an 18% instruction per clock (IPC) improvement over Skylake. Willow Cove, in turn, might improve IPC another 5-10% or so. This would deliver a solid 25% or so increased IPC relative to Skylake.
Aside from yield worries, the peak frequencies for the early versions of 10nm compared to 14nm is also likely to have played a role in choosing 14nm for Rocket Lake. It will be interesting to see what frequencies this new architecture can deliver on Intel’s highly-optimized 14nm process, but it certainly looks like it will bring significant performance improvements.
However, it looks like SGX will be absent. This features, introduced in Skylake, has recently come under attention due to the LVI vulnerability, but has long been an attack vector.
New GPU Architecture, 'Xe'cellent news
Rocket Lake will also bring the new Xe Architecture for integrated graphics (internally codenamed Gen12). This is the same architecture present on both Tiger Lake and DG1. This new architecture will also come with support for both AV1 encode and decode, which is a big deal given how CPU intensive the codec is. This in turn implies that both Tiger Lake and DG1 will also support it, which is great news.
While it has not been confirmed by this leak, previous leaks have indicated a 32EU implementation, which is more than previous Gen9 iterations that come with 24 EUs, but significantly less than Tiger Lake’s 96 EUs. Nevertheless, the combination of Gen12, more EUs and higher frequencies could mean double the integrated graphics performance on desktop.
The slide does not confirm whether the Xe graphics will be a backported 14nm version or, as the Tweakers roadmap suggested, a separate 10nm chiplet. In the case of a 14nm backport, it also could be integrated either on-die or as a chiplet.
I/O: PCIe 4.0, DMI 3.0 x8 and Thunderbolt 4
Rocket Lake-S also has significantly updated I/O, which is an area where AMD has taken the lead with PCIe 4.0 support. Rocket Lake-S is set to level the playing field in that regard, and direct lanes from the CPU go up from 16 to 20, which means both an NVMe drive and GPU will have direct connection. The DMI link from the CPU to chipset has also been increased from x4 to x8, which will double bandwidth to devices connected via chipset. The lanes that hang off the chipset remain at PCIe 3.0, though, which tracks well with our previous reporting that Intel encountered issues with implementing PCIe 4.0 on its chipsets.
There will also be support for Thunderbolt 4, although this does not have a higher speed than Thunderbolt 3, as well as integrated USB 3.2 Gen 2x2.
Other features that are mentioned as new for the Rocket Lake platform are enhanced display capabilities with integrated HDMI 2.0b and DisplayPort 1.4a, enhanced media with 12-bit AV1 and HEVC compression, new overclocking features, increased DDR4 speed and USB audio offload.
I wonder if Intel knows 10th gen is a dude, released at least 18 months after 9th gen and is not close to 11th gen being ready. Never mind it still won't be competitive with Zen 2, nor the upcoming Zen 3. And so they are starting to get the market warmed up for 11th gen.
Also, you have to wonder how much will come out on time (from any vendor) given the pandemic. Delays are for the best; obviously lives matter more than ship dates. Just not reading any timetables the same these days.
PCIe 4 off the CPU, PCIe 3 off the chipset. Tracks well with our previous reporting that Intel had issues implementing PCIe 4.0 in the chipset for Socket 1200 boards (both Comet and Rocket use LGA1200) https://www.tomshardware.com/news/intel-gets-the-jitters-plans-then-nixes-pcie-40-support-on-comet-lake
The PCIe coming directly off the CPU doesn't stipulate which generation, but then the boxes on the side say it's 4.0.
This is entirely independent of what flavor the chipset-connected lanes are. I mean, they already doubled DMI bandwidth while keeping the chipset-connected lanes at 3.0. They could've just done it another, possibly cheaper way.
......more 14nm+++++++++ nonsense?